JPH0963805A - Square chip resistor - Google Patents

Square chip resistor

Info

Publication number
JPH0963805A
JPH0963805A JP7218536A JP21853695A JPH0963805A JP H0963805 A JPH0963805 A JP H0963805A JP 7218536 A JP7218536 A JP 7218536A JP 21853695 A JP21853695 A JP 21853695A JP H0963805 A JPH0963805 A JP H0963805A
Authority
JP
Japan
Prior art keywords
thick film
resistance
resistor
chip resistor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7218536A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yamada
博之 山田
Akio Fukuoka
章夫 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7218536A priority Critical patent/JPH0963805A/en
Publication of JPH0963805A publication Critical patent/JPH0963805A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a square chip resistor which has a low resistance and is excellent in resistance precision. SOLUTION: The square chip resistor consists of the following: a pair of thick film resistor layers 12 formed on an upper surface of a square board 11, thick film upper surface electrode layers 13 electrically connected with the thick film resistor layers 12, and a pair of thick film end surface electrode layers 14 which connect a plurality of resistance elements in parallel. Thereby, a square chip resistor which has a low resistance and is excellent in resistance precision is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種電子回路に用いら
れる角形チップ抵抗器に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectangular chip resistor used in various electronic circuits.

【0002】[0002]

【従来の技術】近年、電子機器の小型化にともない、電
子部品の実装面積を縮小するため、表面実装部品への要
求が高まっている。その中で、角形チップ抵抗器に対し
ても、従来からの半固定ボリュームの代替として、高精
度品への要求が高い。例えば、電源回路での電流検出用
として、低抵抗かつ抵抗値精度に優れた角形チップ抵抗
器などもその要求の一つである。
2. Description of the Related Art In recent years, with the miniaturization of electronic equipment, the demand for surface-mounted components has increased in order to reduce the mounting area of electronic components. Among them, there is a strong demand for high precision products as an alternative to the conventional semi-fixed volume for the rectangular chip resistor. For example, a rectangular chip resistor having low resistance and excellent resistance value accuracy is one of the requirements for detecting current in a power supply circuit.

【0003】以下に、従来の角形チップ抵抗器につい
て、図面を参照しながら説明する。図2は従来の角形チ
ップ抵抗器の斜視図である。図において、1は96%ア
ルミナからなる方形の基板である。2は基板1の上面の
対向する側部のそれぞれに設けられた酸化ルテニウム系
グレーズからなる厚膜抵抗体層である。3は基板1上の
側部のそれぞれに設けられた厚膜抵抗体層2と電気的に
接続するように基板1の上面に設けられたAg系のグレ
ーズからなる厚膜上面電極層である。4は厚膜抵抗体層
2と電気的に接続するように基板1のそれぞれの端面に
設けられたAg系グレーズからなる厚膜端面電極層であ
る。また、厚膜抵抗体層2は、これを覆うように基板1
上にホウケイ酸鉛系ガラスにより厚膜保護膜層(図示せ
ず)を、厚膜上面電極層3と厚膜端面電極層4は、これ
らを覆うようにニッケルおよびはんだによる電極めっき
層(図示せず)とから構成されていた。
A conventional rectangular chip resistor will be described below with reference to the drawings. FIG. 2 is a perspective view of a conventional rectangular chip resistor. In the figure, 1 is a rectangular substrate made of 96% alumina. Reference numeral 2 is a thick-film resistor layer made of ruthenium oxide-based glaze provided on each of opposite sides of the upper surface of the substrate 1. Reference numeral 3 denotes a thick film upper surface electrode layer made of an Ag-based glaze provided on the upper surface of the substrate 1 so as to be electrically connected to the thick film resistor layers 2 provided on the respective side portions of the substrate 1. Reference numeral 4 is a thick film end face electrode layer made of Ag-based glaze provided on each end face of the substrate 1 so as to be electrically connected to the thick film resistor layer 2. Further, the thick film resistor layer 2 covers the substrate 1 so as to cover it.
A thick film protective film layer (not shown) made of lead borosilicate glass is provided on the upper surface, and an electrode plating layer (not shown) made of nickel and solder is formed so as to cover the thick film upper surface electrode layer 3 and the thick film end surface electrode layer 4. )) And.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記従
来の角形チップ抵抗器は、低抵抗値(特に1Ω以下)の
抵抗値精度を良くしようとしても、抵抗値が低いために
抵抗値修正や完成品の抵抗値選別などで、抵抗値測定機
自身の測定精度が得難く、また測定端子と電極間に生ず
る接触抵抗の影響から、抵抗値精度の向上に限界がある
という課題を有していた。
However, the above-mentioned conventional rectangular chip resistor has a low resistance value even if an attempt is made to improve the resistance value accuracy of a low resistance value (particularly 1 Ω or less). However, there is a problem in that it is difficult to obtain the measurement accuracy of the resistance value measuring device itself due to the selection of the resistance value, and the improvement of the resistance value is limited due to the influence of the contact resistance between the measurement terminal and the electrode.

【0005】本発明は上記従来の課題を解決するもの
で、低抵抗で抵抗値精度に優れた角形チップ抵抗器を提
供することを目的とするものである。
The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a rectangular chip resistor having low resistance and excellent resistance value accuracy.

【0006】[0006]

【課題を解決するための手段】上記した目的を達成する
ために本発明は、方形の基板と、この基板の上面に対向
したそれぞれの側部に設けられた複数の厚膜抵抗体層
と、この厚膜抵抗体層のそれぞれに電気的に接続するよ
うに設けられた厚膜上面電極層と、この厚膜上面電極層
と電気的に接続するように基板の端面に設けられた厚膜
端面電極層とからなるものである。
In order to achieve the above-mentioned object, the present invention provides a rectangular substrate, and a plurality of thick film resistor layers provided on respective side portions facing the upper surface of the substrate, A thick film upper surface electrode layer provided so as to be electrically connected to each of the thick film resistor layers, and a thick film end surface provided at an end surface of the substrate so as to be electrically connected to this thick film upper surface electrode layer. It is composed of an electrode layer.

【0007】[0007]

【作用】本発明によれば、複数個の抵抗素子を電極層で
並列に接続することによる合成抵抗値により角形チップ
抵抗器としての抵抗値が形成されることになる。
According to the present invention, a resistance value as a rectangular chip resistor is formed by a combined resistance value obtained by connecting a plurality of resistance elements in parallel with electrode layers.

【0008】[0008]

【実施例】以下、本発明の一実施例における角形チップ
抵抗器について、図面を参照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A rectangular chip resistor according to an embodiment of the present invention will be described below with reference to the drawings.

【0009】図1は本発明の一実施例における角形チッ
プ抵抗器の斜視図である。図において、11は96%ア
ルミナからなる方形の基板である。12は基板11の上
面の対向する側部のそれぞれ4箇所に設けられた酸化ル
テニウム系グレーズからなる厚膜抵抗体層である。13
は基板11の上面に対向する側部のそれぞれ4箇所に設
けられた厚膜抵抗体層12と電気的にそれぞれが接続す
るように設けられたAg系のグレーズからなる厚膜上面
電極層である。14は基板11の上面に設けられた4つ
の厚膜抵抗体層12と相互に電気的に接続するように基
板11のそれぞれの端面に設けられた厚膜端面電極層で
ある。また、4つの厚膜抵抗体層12は、これらを覆う
ようにホウケイ酸鉛系ガラスによる厚膜保護膜(図示せ
ず)で覆われ、厚膜抵抗体層12と厚膜端面電極層14
は、これらを覆うようにニッケルおよびはんだにより電
極めっき層(図示せず)で覆われて構成するものであ
る。
FIG. 1 is a perspective view of a rectangular chip resistor according to an embodiment of the present invention. In the figure, 11 is a rectangular substrate made of 96% alumina. Reference numeral 12 is a thick-film resistor layer made of ruthenium oxide-based glaze, which is provided on each of four opposite sides of the upper surface of the substrate 11. Thirteen
Is a thick film upper surface electrode layer made of an Ag-based glaze provided so as to be electrically connected to the thick film resistor layers 12 respectively provided at four positions on the side facing the upper surface of the substrate 11. . Reference numeral 14 is a thick film end face electrode layer provided on each end face of the substrate 11 so as to be electrically connected to the four thick film resistor layers 12 provided on the upper face of the substrate 11. Further, the four thick film resistor layers 12 are covered with a thick film protective film (not shown) made of lead borosilicate glass so as to cover them, and the thick film resistor layer 12 and the thick film end face electrode layer 14 are covered.
Is composed of an electrode plating layer (not shown) covered with nickel and solder so as to cover them.

【0010】以上のように構成された角形チップ抵抗器
について、以下にその製造方法を説明する。
The manufacturing method of the rectangular chip resistor configured as described above will be described below.

【0011】まず、耐熱性および絶縁性に優れた96%
アルミナを有する基板11の表面にAgを主成分とする
電極ペーストを基板11の上面の対向する側部のそれぞ
れ4箇所にスクリーン印刷し、850℃で焼成し、4つ
の厚膜上面電極層13を形成する。
First, 96% excellent in heat resistance and insulation.
On the surface of the substrate 11 having alumina, an electrode paste containing Ag as a main component was screen-printed on each of four opposite sides of the upper surface of the substrate 11 and baked at 850 ° C. to form four thick film upper electrode layers 13. Form.

【0012】次に、基板11上面に酸化ルテニウム系グ
レーズの抵抗ペーストを対向するそれぞれの厚膜上面電
極層13間に印刷し、850℃で焼成して4つの厚膜抵
抗体層12を形成する。
Next, a ruthenium oxide glaze resistance paste is printed on the upper surface of the substrate 11 between the respective thick film upper surface electrode layers 13 facing each other, and baked at 850 ° C. to form four thick film resistor layers 12. .

【0013】次に、必要に応じて厚膜抵抗体層12の個
々の抵抗値をレーザートリミングにより所定の値に修正
する。
Next, if necessary, the individual resistance values of the thick film resistor layer 12 are corrected to predetermined values by laser trimming.

【0014】次に、抵抗値修正済み厚膜抵抗体層12を
保護するために、ホウケイ酸鉛系ガラスペーストをスク
リーン印刷し、600℃で焼成して保護膜層(図示せ
ず)を形成する。このとき、並列接続される4つの厚膜
抵抗体層12を1つのパターンで覆うこととした。
Next, in order to protect the thick film resistor layer 12 whose resistance value has been corrected, a lead borosilicate glass paste is screen-printed and baked at 600 ° C. to form a protective film layer (not shown). . At this time, the four thick film resistor layers 12 connected in parallel are covered with one pattern.

【0015】次に、基板11の上面に設けた厚膜上面電
極層13と電気的に接続するように基板11の端面にA
g系グレーズによる電極ペーストをローラーにより塗布
し、600℃で焼成して厚膜端面電極層14を形成す
る。このとき、4つの厚膜抵抗体層12と接続する4つ
の厚膜上面電極層13を並列接続するように厚膜端面電
極層14を形成する。
Next, A is formed on the end surface of the substrate 11 so as to be electrically connected to the thick film upper surface electrode layer 13 provided on the upper surface of the substrate 11.
An electrode paste of g-based glaze is applied by a roller and baked at 600 ° C. to form the thick film end face electrode layer 14. At this time, the thick film end face electrode layers 14 are formed so that the four thick film upper surface electrode layers 13 connected to the four thick film resistor layers 12 are connected in parallel.

【0016】最後に、露出している厚膜上面電極層13
と厚膜端面電極層14のはんだ付け時の電極食われの防
止およびはんだ付け時の信頼性の確保のため、電気めっ
きによってNiおよびSn−Pbのめっき層を形成して
角形チップ抵抗器を製造するものである。
Finally, the exposed thick film upper surface electrode layer 13
In order to prevent electrode erosion during soldering of the thick film end face electrode layer 14 and to ensure reliability during soldering, a plating layer of Ni and Sn-Pb is formed by electroplating to manufacture a rectangular chip resistor. To do.

【0017】以上の工程により、本発明による角形チッ
プ抵抗器を試作した。この本発明の角形チップ抵抗器で
は、各抵抗素子が1Ωになるよう抵抗材料を選定し、抵
抗値修正した。したがって、4つの抵抗素子を並列接続
する事により、0.25Ωを形成することができる。従
来0.25Ωの抵抗値精度は±5%程度が限界であった
が、本発明によれば各抵抗素子は1Ωであり±1%の精
度が得られる領域であることで、合成抵抗値0.25Ω
で±1%が達成できた。また、抵抗温度係数も0.25
Ωでありながら、従来+600ppm/℃であったが、
+100ppm/℃にする事ができた。
Through the above steps, a square chip resistor according to the present invention was prototyped. In this rectangular chip resistor of the present invention, a resistance material was selected so that each resistance element was 1Ω, and the resistance value was corrected. Therefore, by connecting four resistance elements in parallel, 0.25Ω can be formed. Conventionally, the resistance value accuracy of 0.25Ω was limited to about ± 5%, but according to the present invention, since each resistance element is 1Ω and the region where the accuracy of ± 1% is obtained, the combined resistance value 0 0.25 Ω
Within ± 1% was achieved. Also, the temperature coefficient of resistance is 0.25
Although it was Ω, it was + 600ppm / ° C in the past,
It could be +100 ppm / ° C.

【0018】なお、本実施例では厚膜端面電極層により
複数の抵抗素子を並列接続したが、端面電極層以外で抵
抗素子を並列接続してもよく、その目的とする抵抗値よ
りも高い抵抗値を持つ抵抗素子を並列接続して低抵抗値
を実現しても良い。
In this embodiment, the plurality of resistance elements are connected in parallel by the thick film end face electrode layer, but the resistance elements may be connected in parallel other than the end face electrode layer, and the resistance value higher than the target resistance value may be used. A low resistance value may be realized by connecting resistance elements having different values in parallel.

【0019】また、本実施例では厚膜抵抗素子について
説明したが、構成する材料を制限するものではなく、薄
膜抵抗素子でも同様である。
Further, although the thick film resistance element has been described in the present embodiment, the constituent material is not limited, and the same applies to the thin film resistance element.

【0020】また、並列接続された抵抗素子を1つのパ
ターンの保護膜で覆ったが、パターンを個別に形成して
も良い。
Although the resistance elements connected in parallel are covered with the protective film having one pattern, the patterns may be formed individually.

【0021】また、本実施例では4つの厚膜抵抗体層お
よび厚膜上面電極層について説明したが、これは所望の
抵抗器により設ける厚膜抵抗体層および厚膜上面電極層
を複数備えれば良い。
Although four thick film resistor layers and thick film upper surface electrode layers have been described in the present embodiment, a plurality of thick film resistor layers and thick film upper surface electrode layers provided by desired resistors are provided. Good.

【0022】[0022]

【発明の効果】以上のように本発明は、電極層で複数個
の抵抗素子を並列に接続することによる合成抵抗値によ
り、角形チップ抵抗器としての抵抗値が形成されること
になるので、従来から独立した一つの抵抗体で形成して
いた抵抗値と同じ抵抗値を形成した場合には、従来より
も各抵抗素子の抵抗値が高くなることとなり、接触抵抗
の影響を受けにくくなり、抵抗値修正工程での測定精度
が得やすいと共に、各抵抗素子の抵抗値精度が良けれ
ば、これらの合成抵抗値の精度はさらに良くなることか
ら、従来よりも低抵抗値ながら抵抗値精度を良くするこ
とが可能となる角形チップ抵抗器が提供できるものであ
る。
As described above, according to the present invention, a resistance value as a rectangular chip resistor is formed by a combined resistance value obtained by connecting a plurality of resistance elements in parallel in the electrode layer. When the same resistance value as the resistance value formed by one independent resistor from the past is formed, the resistance value of each resistance element becomes higher than in the conventional case, and it is less likely to be affected by the contact resistance. If the measurement accuracy in the resistance value correction process is easy to obtain and the resistance value accuracy of each resistance element is good, the accuracy of these combined resistance values will be even better. It is possible to provide a rectangular chip resistor that can achieve the above.

【0023】また、抵抗体を形成する抵抗材料も従来よ
りも面積抵抗値の高いものを使用することになるので、
低抵抗を有する材料よりも高抵抗を有する材料の方が、
抵抗温度係数を制限しやすいことから、抵抗温度係数に
ついても抵抗値精度と同様、良好にすることが可能であ
る角形チップ抵抗器を提供できるものである。
Further, since the resistance material for forming the resistor has a higher area resistance value than the conventional one,
A material having a high resistance is better than a material having a low resistance.
Since it is easy to limit the temperature coefficient of resistance, it is possible to provide a rectangular chip resistor capable of improving the temperature coefficient of resistance as well as the accuracy of the resistance value.

【0024】また、抵抗素子を並列接続しているので、
負荷を印加した際の抵抗体での負荷集中点(ホットスポ
ット)が従来のように、1点集中ではなく、分散される
ことで寿命特性も良好な角形チップ抵抗器を提供できる
ものである。
Further, since the resistance elements are connected in parallel,
It is possible to provide a rectangular chip resistor having good life characteristics because the load concentration points (hot spots) in the resistor when a load is applied are dispersed instead of being concentrated at one point as in the conventional case.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における角形チップ抵抗器の
斜視図
FIG. 1 is a perspective view of a rectangular chip resistor according to an embodiment of the present invention.

【図2】従来の角形チップ抵抗器の斜視図FIG. 2 is a perspective view of a conventional rectangular chip resistor.

【符号の説明】[Explanation of symbols]

11 基板 12 厚膜抵抗体層 13 厚膜上面電極層 14 厚膜端面電極層 11 Substrate 12 Thick Film Resistor Layer 13 Thick Film Top Electrode Layer 14 Thick Film End Face Electrode Layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 方形の基板と、この基板の上面に対向し
たそれぞれの側部に設けられた複数の厚膜抵抗体層と、
この複数厚膜抵抗体層のそれぞれに電気的に接続するよ
うに前記基板上に設けられた厚膜上面電極層と、この厚
膜上面電極層と相互に電気的に接続するように前記基板
の端面に設けられた厚膜端面電極層とからなる角形チッ
プ抵抗器。
1. A rectangular substrate, and a plurality of thick film resistor layers provided on respective sides facing the upper surface of the substrate,
A thick film upper surface electrode layer provided on the substrate so as to be electrically connected to each of the plurality of thick film resistor layers, and the thick film upper surface electrode layer of the substrate so as to be electrically connected to each other. A rectangular chip resistor comprising a thick film end face electrode layer provided on the end face.
JP7218536A 1995-08-28 1995-08-28 Square chip resistor Pending JPH0963805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7218536A JPH0963805A (en) 1995-08-28 1995-08-28 Square chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7218536A JPH0963805A (en) 1995-08-28 1995-08-28 Square chip resistor

Publications (1)

Publication Number Publication Date
JPH0963805A true JPH0963805A (en) 1997-03-07

Family

ID=16721472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7218536A Pending JPH0963805A (en) 1995-08-28 1995-08-28 Square chip resistor

Country Status (1)

Country Link
JP (1) JPH0963805A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043717A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Electronic parts and its manufacturing method
US6873028B2 (en) * 2001-11-15 2005-03-29 Vishay Intertechnology, Inc. Surge current chip resistor
WO2007029635A1 (en) * 2005-09-06 2007-03-15 Rohm Co., Ltd. Chip resistor and method for producing the same
JP2007073694A (en) * 2005-09-06 2007-03-22 Rohm Co Ltd Chip resistor and method of manufacturing same
WO2023089899A1 (en) * 2021-11-18 2023-05-25 ローム株式会社 Chip resistor module

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043717A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Electronic parts and its manufacturing method
JP4547781B2 (en) * 2000-07-28 2010-09-22 パナソニック株式会社 Method for manufacturing multiple chip resistors
US6873028B2 (en) * 2001-11-15 2005-03-29 Vishay Intertechnology, Inc. Surge current chip resistor
WO2007029635A1 (en) * 2005-09-06 2007-03-15 Rohm Co., Ltd. Chip resistor and method for producing the same
JP2007073694A (en) * 2005-09-06 2007-03-22 Rohm Co Ltd Chip resistor and method of manufacturing same
JP2007073693A (en) * 2005-09-06 2007-03-22 Rohm Co Ltd Chip resistor and method of manufacturing same
US7907046B2 (en) 2005-09-06 2011-03-15 Rohm Co., Ltd. Chip resistor and method for producing the same
WO2023089899A1 (en) * 2021-11-18 2023-05-25 ローム株式会社 Chip resistor module

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