JPS59113613A - Method of forming end race electrode - Google Patents

Method of forming end race electrode

Info

Publication number
JPS59113613A
JPS59113613A JP22422382A JP22422382A JPS59113613A JP S59113613 A JPS59113613 A JP S59113613A JP 22422382 A JP22422382 A JP 22422382A JP 22422382 A JP22422382 A JP 22422382A JP S59113613 A JPS59113613 A JP S59113613A
Authority
JP
Japan
Prior art keywords
layer
capacitor
forming
conductive layer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22422382A
Other languages
Japanese (ja)
Inventor
博史 山口
涼 木村
久子 森
寛敏 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22422382A priority Critical patent/JPS59113613A/en
Publication of JPS59113613A publication Critical patent/JPS59113613A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ラジオ受信機、テープレコーダ、ポータプル
ビデオ等の民生用電子機器回路に用いることができる複
合回路部品の端面電極の形成方法に関するものである゛
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of forming end face electrodes of composite circuit components that can be used in consumer electronic equipment circuits such as radio receivers, tape recorders, portable videos, etc.゛.

従来例の構成とその問題点 近年、ラジオ受信機、テープレコード、ポータプルビデ
オ等の民生用電子機器回路の超小型化の進む中で、モノ
リシックICの内部に組込むことの困難なインダクタ、
高精度抵抗、大容量キャパシタなどの受動素子の処理が
、アナログ回路の高集積化への障害になっており、それ
ら受動素子の効率的な実装が、超小型化への鍵を握って
いる。
Conventional configurations and their problems In recent years, as the circuits of consumer electronic devices such as radio receivers, tape records, and portable videos have become increasingly miniaturized, inductors, which are difficult to incorporate into monolithic ICs,
The processing of passive elements such as high-precision resistors and large-capacity capacitors has become an obstacle to higher integration of analog circuits, and efficient implementation of these passive elements holds the key to ultra-miniaturization.

この目的のために、比体積容量の大きいという特徴を有
する積層セラミックコンデンサを、さらに複合化した積
層複合コンデンサをベーメ基板にして、この上にトリミ
ングなどによシ高精度かっ安定な特性を得ることのでき
る厚膜抵抗回路を形成した複合回路部品が提案されてい
る。この場合、積層複合コンデンサの引出し端子は側面
に形成されているが、この端子とコンデンサ基板上に設
けた抵抗回路との接続のため、及び、上、下両面回路の
導通を得るため、さらには、外部回路への実装上の引出
し端子電極として、縁端面に導電層を形成する必要があ
る。また、上、下、側面にわたる配線と、積層コンデン
サの内部電極との間に、その高い誘電率の故に高い浮遊
容量を発生するため、配線用の導電体層下に、低誘電率
誘電体層を設けることによりこれを低減することも、特
性確保上必要になる。
For this purpose, a multilayer ceramic capacitor, which is characterized by a large specific volumetric capacitance, is further combined with a multilayer composite capacitor as a Boehme substrate, and on this board, by trimming etc., high precision and stable characteristics can be obtained. Composite circuit components formed with thick film resistor circuits have been proposed. In this case, the extraction terminal of the multilayer composite capacitor is formed on the side surface, and in order to connect this terminal with the resistance circuit provided on the capacitor board, and to obtain continuity between the upper and lower surface circuits, , it is necessary to form a conductive layer on the edge surface as a lead-out terminal electrode for mounting on an external circuit. In addition, high stray capacitance occurs between the wiring that spans the top, bottom, and sides and the internal electrodes of the multilayer capacitor due to its high dielectric constant. It is also necessary to reduce this by providing .

従来、此種の方法としてはスクリーン印刷法が一般的で
ある。まず、積層複合コンデンサの上。
Conventionally, screen printing has been commonly used as this type of method. First, on the laminated composite capacitor.

下、側面に、順次、シルクスクリーン又はステンレスス
クリーンを使用したスクリーン印刷によって、未焼成状
態の低誘電率誘電体ペーストにて、基板側面のコンデン
サ端子部を除いて低誘電率誘電体層を塗布形成し、加熱
乾燥後焼成する。ついで、同様にして未焼成状態の導電
体ペーストにて、上、下、側面に導電層を形成し、加熱
乾燥後焼成してこの工程は完了する。
On the bottom and side surfaces, a low-permittivity dielectric layer is sequentially applied using unfired low-permittivity dielectric paste by screen printing using a silk screen or stainless steel screen, except for the capacitor terminals on the side of the board. Then, after heating and drying, it is fired. Next, conductive layers are similarly formed on the top, bottom, and side surfaces using unfired conductive paste, and the process is completed by heating and drying and firing.

しかしながらこの方法は、互いに直交する二面上の層を
、平面印刷の組合わせによって基板のエツジ部でのペー
ストのたれによってのみ接続し、電気的導通を得ようと
するものであり、通常接続に必要とされる合わせ余裕は
零で、根本的に無理を伴っており、必然的に信頼性に乏
しく、かつ技術的に困難であり生産性も乏しい。また、
エツジ部での直角性の不完全さによるにじみからのショ
ートの可能性を内包しており、導体層と誘電体層の二層
間の位置合わせが多数回におよぶために、位置ずれによ
る不良発生の可能性が累積されるという問題もある。こ
れら、端面電極の形成に伴う困難の故に、前述の高精度
抵抗−複合大容量コンデンサの複合回路部品は、その有
効性が認められつつも、提案にとどまっているのが現状
である。
However, this method attempts to connect layers on two mutually perpendicular surfaces only by dripping paste at the edge of the board by a combination of flat printing, and to obtain electrical continuity, which is not a normal connection. The required alignment margin is zero, it is fundamentally unreasonable, it is necessarily unreliable, and it is technically difficult and has poor productivity. Also,
This includes the possibility of short circuits due to bleeding due to imperfect perpendicularity at edges, and since alignment between the two layers of the conductor layer and dielectric layer is repeated many times, there is a risk of defects due to misalignment. There is also the issue of cumulative probabilities. Due to these difficulties associated with the formation of end face electrodes, the above-mentioned composite circuit component of a high-precision resistor-composite large-capacitance capacitor, although its effectiveness has been recognized, remains as a proposal at present.

発明の目的 本発明の目的は、抵抗−コンデンサ複合回路部品の端面
電極形成上の上記問題点を排し、簡便かつ確実にこれを
行う方法を提供することにある。
OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems in forming end face electrodes of a resistor-capacitor composite circuit component and to provide a method for doing so simply and reliably.

発明の構成 本発明の端面電極の形成方法は、離型処理されたベース
フィルム上に所望の形状に導電体層を形成し、この上に
前記導電体層を覆うごとく低誘電率誘電体層を形成し、
更に前記低誘電率誘電体層を覆うごとく熱可塑性樹脂層
を形成して多層フィルムを用意し、この多層フィルムを
、複数の対面電極を高誘電率誘電体層を介して積層しか
つ側面に引出し電極を設けたセラミック積層複合コンデ
ンサの側面に、少くとも前記導電体層の一部が両生面に
張り出すようにして加熱圧着し、前記ベースフィルムを
剥離した後、焼成するものであり、従来エツジ部でなさ
ざるを得なかった回路接続を、平面部で行うことを可能
にすることで充分な合わせ余裕を確保し、また複数回に
およぶ側面への印刷工程を排することで、作業性、信頼
性を大きく向上させるものである。
Structure of the Invention The method for forming an end face electrode of the present invention involves forming a conductive layer in a desired shape on a base film that has been subjected to mold release treatment, and then depositing a low dielectric constant dielectric layer on top of the conductive layer so as to cover the conductive layer. form,
Furthermore, a thermoplastic resin layer is formed to cover the low-permittivity dielectric layer to prepare a multilayer film, and this multilayer film is laminated with a plurality of facing electrodes via a high-permittivity dielectric layer and drawn out on the side. The conductive layer is heat-pressed onto the side surface of a ceramic multilayer composite capacitor provided with electrodes so that at least a portion of the conductive layer protrudes on both surfaces, and after the base film is peeled off, it is fired. By making it possible to make circuit connections on the flat surface instead of the circuits that had to be made on the front surface, a sufficient alignment margin is secured, and by eliminating the multiple printing process on the side surface, workability is improved. This greatly improves reliability.

実施例の説明 以下、本発明の一実施例を図面を参照しながら説明する
。第1図(a)、 (b)は本β明に用いる多層フィル
ムの平面図と、X−X/面の断面図であり、同図に示す
ように、後の工程で剥離可能なように離型処理されたポ
リエステルベースフィルム1の上に、まず第一層として
スクリーン印刷により、銀20%−パラジウム80%の
未焼成導電体ペーストにて、基板厚みを超える長さを有
する導電体層のパターン2を形成し、加熱、乾燥する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Figures 1 (a) and (b) are a plan view and a cross-sectional view taken along the plane X-X of the multilayer film used in the present β film. On the release-treated polyester base film 1, a conductive layer having a length exceeding the thickness of the substrate is formed as a first layer using an unfired conductive paste of 20% silver and 80% palladium by screen printing. Pattern 2 is formed, heated and dried.

この導電体層は、後に抵抗−コンデンサ複合回路部品の
端子電極となるものであるが、回路的に、単に上下面回
路の導通を得るだめのものと、基板内に構成されている
コンデンサ、との導通を、側面に設けられたコンデンサ
の引出し電極3と接続することで得るものとがある。次
に第二層として、複合コンデンサの側面端子との接続を
もたない導電体層を完全に覆うように、ガラスペースト
にて低誘電率誘電体層4を塗布形成し、加熱、乾燥する
This conductive layer will later become the terminal electrode of the resistor-capacitor composite circuit component, but from a circuit perspective, there are two types of conductive layers: one for simply providing continuity between the upper and lower circuits, and the other for the capacitor constructed within the board. In some cases, electrical conduction is obtained by connecting to the lead electrode 3 of a capacitor provided on the side surface. Next, as a second layer, a low-permittivity dielectric layer 4 is formed by applying glass paste so as to completely cover the conductive layer that has no connection to the side terminals of the composite capacitor, and is heated and dried.

これは、端面電極と基板内部の電極との間の浮遊容量を
低減するだめのものである。この時、複合コンデンサの
側面端子との接続をもつ導体層上には、その導通のため
に誘電体層は設けないが、この時化ずる浮遊容量は、も
ともとある大容量に付加されるもので問題にならない。
This is to reduce the stray capacitance between the end face electrode and the electrode inside the substrate. At this time, a dielectric layer is not provided on the conductor layer that is connected to the side terminal of the composite capacitor for continuity, but the stray capacitance that increases at this time is added to the already large capacitance. It's not a problem.

さらに、第三層として、ポリアミド樹脂により、後工程
の加熱圧着時に導電体層2.低誘電率誘電体層4の基板
への接着に寄与する熱可塑性樹脂層6を塗布形成。
Furthermore, as a third layer, a conductive layer 2.0 is formed using polyamide resin during heat compression bonding in a post-process. A thermoplastic resin layer 6 that contributes to adhesion of the low dielectric constant dielectric layer 4 to the substrate is formed by coating.

乾燥し、多層フィルムは完成する。この時、導電体ヘー
スト、誘電体ペーストには、エチルセルロースを混入し
乾燥後の柔軟性及び層相互の接着性を確保している。
After drying, the multilayer film is completed. At this time, ethyl cellulose is mixed into the conductive paste and the dielectric paste to ensure flexibility after drying and adhesion between the layers.

上記多層フィルムを、第2図に示すように、所定の位置
合わせの後、複合コンデンサ基板6の側面部及び上、下
面にわたってコの字状に加熱圧着する。このとき、熱可
塑性樹脂層5は加熱により融解し粘着性を示し、ベース
フィルム1はその離型性により容易に剥離され、導電体
層及び低誘電率誘電体層が、複合コンデンサ縁端部にコ
の字状に形成される。これを85C)C大気中で焼成す
ることにより、複合コンデンサ基板上への端面電極の形
成が完了する。
As shown in FIG. 2, after predetermined alignment, the multilayer film is heat-pressed in a U-shape over the side, upper and lower surfaces of the composite capacitor substrate 6. At this time, the thermoplastic resin layer 5 is melted by heating and exhibits adhesiveness, and the base film 1 is easily peeled off due to its releasability, and the conductor layer and low-permittivity dielectric layer are attached to the edge of the composite capacitor. It is formed in a U-shape. By firing this in an 85C)C atmosphere, the formation of the end electrodes on the composite capacitor substrate is completed.

以下、標準的な厚膜プロセスにより、上、下面に低誘電
率誘電体層を塗布形成後抵抗回路を形成することで、平
面部において確実な接続を得、従来法におけるエツジ部
での接続不安を解消し、また、作業上の困難も伴なわず
に抵抗、コンデンサ複合回路部品を完成することができ
る。
After applying a low-permittivity dielectric layer to the top and bottom surfaces using a standard thick film process, a resistor circuit is formed to obtain a reliable connection on the flat surface, eliminating the connection concerns at the edges of the conventional method. In addition, resistor and capacitor composite circuit components can be completed without any operational difficulties.

なお、本実施例では導電材料として銀−ノくラジウムを
用いたが、他に金、銀、銅、銀−白金でもよく、第三層
にはポリアミド以外でも、加熱圧着時に融解し粘着性を
示すものなら何でもよく、ペーストに混入する有機物は
、柔軟性と接着性を持たせ得るものであれば、エチルセ
ルロースに限定するものではない。また、焼成温度を8
50℃としたが、これはペーストその他とのかね合いで
、500℃〜120o℃の範囲で適当な値に選択し得る
。ここで下限を500℃としたのは、それ以下であると
ガラス成分の融解に支障をきたすためであり、上限を1
20C)Cとしたのは、それ以上だと複合コンデンサに
特性劣化が生ずるためである。
In this example, silver-platinum was used as the conductive material, but gold, silver, copper, or silver-platinum may also be used, and the third layer may also be made of other than polyamide, which melts during heat-pressing and becomes sticky. The organic substance mixed into the paste is not limited to ethyl cellulose as long as it can impart flexibility and adhesiveness. Also, the firing temperature was set to 8
Although the temperature was set at 50°C, this value may be selected as an appropriate value within the range of 500°C to 120°C depending on the paste and other components. The reason why the lower limit was set at 500°C is that if the temperature is lower than that, it will interfere with the melting of the glass components, so the upper limit is set at 1.
The reason why it is set to 20C) is that if it exceeds that value, the characteristics of the composite capacitor will deteriorate.

また、上、下、側面の電気回路の展開パタンを厚膜で形
成した多層フィルムを構成することにより、全回路、又
は任意の一部を一時に形成することも可能なことは、容
易に類推できる。
In addition, it is easy to infer by analogy that by constructing a multilayer film in which the developed pattern of the upper, lower, and side electrical circuits is formed using a thick film, it is possible to form the entire circuit or any part of it at once. can.

発明の効果 以上の説明から明らかなように本発明の製造方法は、多
層フィルムを用いて、加熱圧着により上板の上、下、側
面にわたって低誘電率誘電体層を同時に形成するので、
従来法における側面への再度にわたる印刷工程を排し、
上、下面回路との接続を充分な合わせ余裕のもとで行う
ことを可能にし、エツジ部での接続に伴う作業性の悪さ
2歩留りの悪さを克服し、端面電極の形成における量産
性、信頼性を大きく向上させ、大容量−高精度抵抗の複
合回路部品の実用化に寄与するものである。
Effects of the Invention As is clear from the above explanation, the manufacturing method of the present invention uses a multilayer film to simultaneously form a low dielectric constant dielectric layer over the upper, lower, and side surfaces of the upper plate by heat and pressure bonding.
Eliminates the process of printing on the sides again in conventional methods,
It makes it possible to connect the upper and lower circuits with sufficient mating margin, overcomes the poor workability and poor yield associated with connections at the edges, and improves mass productivity and reliability in forming edge electrodes. This greatly improves the performance and contributes to the practical use of large-capacity, high-precision resistor composite circuit components.

これによって、民生用機器回路の超小型化の障害となっ
ていた受動素子の実装をより効率的にし、それを実現す
る道を開くものである。
This will pave the way to more efficient mounting of passive elements, which has been an obstacle to the miniaturization of consumer device circuits, and to realize this goal.

さらに最近は、複合コンデンサ基板にインダクタをも一
体焼結する試みもなされており、これが実用ベースに乗
ればLCR一体形モジュールの実現も、本発明の方法を
用いることで可能になり、超小型化のより一層の進展に
寄与することが期待される。
Furthermore, recently, attempts have been made to integrally sinter an inductor onto a composite capacitor substrate, and if this becomes practical, it will be possible to realize an LCR integrated module by using the method of the present invention, which will lead to ultra-miniaturization. It is expected that this will contribute to further progress in the field.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、 (b)は本発明の一実施例に用いる多
層フィルムの平面図とX−Xtにおける断面図、第2図
は端面電極を形成した複合回路部品の要部斜視図である
。 1・・・・・・ベースフィルム、2・・・・・・導電体
層、3・・・・・・複合コンデンサ端子電極、4・・・
・・・低誘電率誘電体層、6・・・・・・熱可塑性樹脂
層、6・・・・・・複合コンデンサ基板。
Figures 1 (a) and (b) are a plan view and a cross-sectional view taken along line X-Xt of a multilayer film used in an embodiment of the present invention, and Figure 2 is a perspective view of the main parts of a composite circuit component on which end electrodes are formed. be. DESCRIPTION OF SYMBOLS 1...Base film, 2...Conductor layer, 3...Composite capacitor terminal electrode, 4...
. . . Low dielectric constant dielectric layer, 6 . . . Thermoplastic resin layer, 6 . . . Composite capacitor substrate.

Claims (3)

【特許請求の範囲】[Claims] (1)離型処理されたベースフィルム上に所望の形状に
導電体層を形成し、この上に前記導電体層を覆うごとく
低誘電率誘電体層を形成し、更に前記低誘電率誘電体層
を覆うごとく熱可塑性樹脂層を形成して多層フィルムを
用意し、この多層フィルムを、複数の対面電極を高誘電
率誘電体層を介して積層しかつ側面に引出し電極を設け
たセラミック積層複合コンデンサの側面に、少くとも前
記導電体層の一部が両生面に張り出すようにして加熱圧
着し、前記ベースフィルムを剥離した後、焼成すること
を特徴とする端面電極の形成方法。
(1) Form a conductive layer in a desired shape on a release-treated base film, form a low dielectric constant dielectric layer thereon so as to cover the conductive layer, and further form the low dielectric constant dielectric layer on the conductive layer so as to cover the conductive layer. A multilayer film is prepared by forming a thermoplastic resin layer so as to cover the layers, and this multilayer film is then laminated with multiple facing electrodes via a high-permittivity dielectric layer, and an extraction electrode is provided on the side. 1. A method for forming an end face electrode, which comprises heat-pressing the conductor layer to a side surface of a capacitor so that at least a part of the conductor layer projects on both sides, peeling off the base film, and then firing the conductor layer.
(2)導電体層の材料として、金、銀、銅、銀−パラジ
ウムおよび銀−白金から選ばれた一種を用いる特許請求
の範囲第(1)項記載の端面電極の形成方法。
(2) The method for forming an end electrode according to claim (1), using one selected from gold, silver, copper, silver-palladium, and silver-platinum as the material of the conductor layer.
(3)焼成温度を600℃〜1200’Cとする特許請
求の範囲第(1)項まだは第(2)項記載の端面電極の
形成方法。
(3) A method for forming an end electrode according to claim (1) or claim (2), wherein the firing temperature is 600°C to 1200'C.
JP22422382A 1982-12-20 1982-12-20 Method of forming end race electrode Pending JPS59113613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22422382A JPS59113613A (en) 1982-12-20 1982-12-20 Method of forming end race electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22422382A JPS59113613A (en) 1982-12-20 1982-12-20 Method of forming end race electrode

Publications (1)

Publication Number Publication Date
JPS59113613A true JPS59113613A (en) 1984-06-30

Family

ID=16810432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22422382A Pending JPS59113613A (en) 1982-12-20 1982-12-20 Method of forming end race electrode

Country Status (1)

Country Link
JP (1) JPS59113613A (en)

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