JPH0632378B2 - Multi-layer ceramic board with built-in electronic components - Google Patents
Multi-layer ceramic board with built-in electronic componentsInfo
- Publication number
- JPH0632378B2 JPH0632378B2 JP60130647A JP13064785A JPH0632378B2 JP H0632378 B2 JPH0632378 B2 JP H0632378B2 JP 60130647 A JP60130647 A JP 60130647A JP 13064785 A JP13064785 A JP 13064785A JP H0632378 B2 JPH0632378 B2 JP H0632378B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- electronic component
- multilayer ceramic
- built
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、多層セラミック基板内に、例えばコンデン
サ、抵抗器、コイル等のチップ形電子部品を内蔵した電
子部品内蔵多層セラミック基板に関する。Description: TECHNICAL FIELD The present invention relates to an electronic component built-in multilayer ceramic substrate in which chip type electronic components such as capacitors, resistors, and coils are built in the multilayer ceramic substrate.
電子回路をより高密度化、多機能化する等のために、電
子部品を内蔵した多層基板が要望されている。In order to make electronic circuits more dense and have more functions, there is a demand for a multilayer substrate containing electronic components.
そのような多層基板の１つに、グリーンシート各層に誘
電体ペースト、絶縁体ペースト、導電ペースト等を厚膜
技術で印刷後、各層を圧着して焼成することによりＬ、
Ｃ、Ｒ回路等を構成したものがある。しかしこのような
多層基板においては、圧着・焼成過程でペーストの変
形が起こるため、抵抗値や静電容量等のＬ、Ｃ、Ｒの特
性を計算通りにすることが困難であること、使用可能
な誘電体ペーストの誘電率が小さくて大容量コンデンサ
の形成が困難であること、絶縁体ペーストの比抵抗を
幅広く選択することが困難であること、印刷積層を繰
り返すに従って印刷部の平面性が非常に悪くなって積層
数を増やすことが困難であること、等の種々の問題があ
る。By printing a dielectric paste, an insulating paste, a conductive paste, etc. on each layer of the green sheet by a thick film technique on one of such multilayer substrates, and then pressing and firing each layer, L,
There are some which have C, R circuits and the like. However, in such a multilayer substrate, it is difficult to make the characteristics of L, C, and R such as resistance and capacitance as calculated because the deformation of the paste occurs during the pressure bonding and firing process. Since it is difficult to form a large-capacity capacitor due to the low dielectric constant of the dielectric paste, it is difficult to select a wide range of specific resistance of the insulating paste, and the flatness of the printed part becomes extremely high as the printing lamination is repeated. However, there are various problems such as that it becomes difficult to increase the number of laminated layers.
一方、従来の多層基板の他の例として、いわゆる抵抗・
容量付多量基板がある（例えば「エレクトロニク・セラ
ミクス」′８５ ５月号 頁６８〜６９参照）。これ
は、セラミックベースの表面にコンデンサ、抵抗器等を
厚膜技術で多層に印刷形成したものである。しかしこの
ような多層基板においても、印刷パターンの位置ずれ
による特性のばらつき、コンデンサ容量の制約、平
面性の悪化、等の上述した多層基板とほぼ同様の問題が
ある。On the other hand, as another example of the conventional multilayer substrate, a so-called resistor
There are large-capacity substrates with capacitors (see, for example, "Electronic Ceramics"'85 May issue, pages 68 to 69). This is one in which capacitors, resistors, etc. are printed and formed in multiple layers by a thick film technique on the surface of a ceramic base. However, even in such a multilayer substrate, there are almost the same problems as those of the above-described multilayer substrate, such as variations in characteristics due to positional deviation of print patterns, restrictions on capacitor capacitance, and deterioration of flatness.
従ってこの発明は、上述のような問題点を解消すること
ができる電子部品内蔵多層セラミック基板を提供するこ
とを目的とする。Therefore, an object of the present invention is to provide an electronic component-embedded multilayer ceramic substrate which can solve the above-mentioned problems.
この発明の電子部品内蔵多層セラミック基板は、凹部ま
たは貫通孔を有するセラミック基板を含む複数枚のセラ
ミック基板であっていずれも非還元性のセラミックから
成るものが一体的に焼成積層されて成る多層セラミック
基板と、この多層セラミック基板内であって前記凹部ま
たは貫通孔で形成される空間内に収納された非還元性の
チップ形電子部品と、前記多層セラミック基板の層間ま
たは前記貫通孔内に設けられていて前記チップ形電子部
品を配線している卑金属から成る導体とを備えることを
特徴とする。The multilayer ceramic substrate with a built-in electronic component of the present invention is a multi-layer ceramic substrate including a ceramic substrate having a recess or a through hole, all of which are made of non-reducing ceramic and are integrally fired and laminated. A substrate, a non-reducing chip-type electronic component housed in the space formed by the recess or the through hole in the multilayer ceramic substrate, and provided in an interlayer of the multilayer ceramic substrate or in the through hole. And a conductor made of a base metal for wiring the chip-type electronic component.
第１図はこの発明の一実施例に係る電子部品内蔵多層セ
ラミック基板を示す概略断面図であり、第２図はその等
価回路図である。貫通孔７をそれぞれ有するセラミック
基板２１〜２５と貫通孔を有さないセラミック基板２６
とが積層されて多層セラミック基板２が形成されてお
り、当該多層セラミック基板２内であって各セラミック
基板の貫通孔７の組み合わせで形成される空間内に、チ
ップ形の受動素子等の電子部品、例えば積層タイプのコ
ンデンサ３、４及び抵抗器５が収納されている。そして
当該コンデンサ３、４及び抵抗器５は、多層セラミック
基板２の層間や貫通孔７内に設けられた導体６で適宜配
線されて第２図に示すような回路を構成している。この
場合、各電子部品を収納する空間を、貫通孔７の代わり
に各セラミック基板２１〜２６に適宜設けた凹部で形成
するようにしても良い。詳細は以下に説明するが、上記
各セラミック基板２１〜２６は、還元雰囲気中で焼成し
ても還元されない（即ち特性劣化を生じない）非還元性
のセラミックから成り、これらが一体的に焼成積層され
て上記多層セラミック基板２が形成されている。上記コ
ンデンサ３、４および抵抗器５も非還元性のものであ
る。上記導体６は卑金属から成る。FIG. 1 is a schematic sectional view showing a multilayer ceramic substrate with a built-in electronic component according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. Ceramic substrates 21 to 25 each having a through hole 7 and a ceramic substrate 26 having no through hole
Are laminated to form a multilayer ceramic substrate 2, and electronic components such as chip-shaped passive elements are provided in the space formed by the combination of the through holes 7 of each ceramic substrate in the multilayer ceramic substrate 2. , For example, multilayer type capacitors 3 and 4 and a resistor 5 are housed. The capacitors 3 and 4 and the resistor 5 are appropriately wired by conductors 6 provided between the layers of the multilayer ceramic substrate 2 and in the through holes 7 to form a circuit as shown in FIG. In this case, the space for accommodating each electronic component may be formed by a recess appropriately provided in each of the ceramic substrates 21 to 26 instead of the through hole 7. As will be described in detail below, each of the ceramic substrates 21 to 26 is made of a non-reducing ceramic that is not reduced (that is, does not cause characteristic deterioration) even when fired in a reducing atmosphere, and these are fired and laminated integrally. Thus, the multilayer ceramic substrate 2 is formed. The capacitors 3 and 4 and the resistor 5 are also non-reducing ones. The conductor 6 is made of base metal.
上述のような電子部品内蔵多層セラミック基板の製法の
一例を第３図を参照して説明する。還元雰囲気中で低温
焼結可能なセラミックのグリーンシート２１Ｇ〜２６Ｇ
の内のグリーンシート２１Ｇ〜２５Ｇのそれぞれに、図
示のように収納するコンデンサ３、４、抵抗器５の形状
・寸法およびそれらの配線パターンに応じた位置に大小
の貫通孔７を予め幾つか空けておき、そして非還元性の
コンデンサ３、４及び非還元性の抵抗器５を予めチップ
部品として完成させておいたものを、前記貫通孔７によ
って形成される空間内に挿入し、また卑金属から成る導
電ペースト６Ｐを各グリーンシート２１Ｇ〜２６Ｇの貫
通孔７の部分や層間の所定の箇所に付与した後、各グリ
ーンシート２１Ｇ〜２６Ｇを圧着し、そして還元雰囲気
中において低温焼成すると、第１図に示した電子部品内
蔵多層セラミック基板が得られる。尚、第３図中の３
１、４１、５１は、それぞれ、チップ形のコンデンサ
３、４及び抵抗器５の外部電極であり、５２はセラミッ
ク基板の表面に付与された抵抗パターンである。An example of a method of manufacturing the above-described multilayer ceramic substrate with built-in electronic components will be described with reference to FIG. Ceramic green sheets 21G to 26G that can be sintered at low temperature in a reducing atmosphere
In each of the green sheets 21G to 25G, several large and small through holes 7 are preliminarily formed at positions corresponding to the shapes and dimensions of the capacitors 3 and 4 and the resistor 5 to be housed as illustrated and their wiring patterns. The non-reducing capacitors 3 and 4 and the non-reducing resistor 5 that have been completed as chip parts in advance are inserted into the space formed by the through hole 7, and are made of base metal. After applying the conductive paste 6P to the through holes 7 of the green sheets 21G to 26G and to predetermined positions between layers, the green sheets 21G to 26G are pressure-bonded and fired at a low temperature in a reducing atmosphere. The multilayer ceramic substrate with a built-in electronic component shown in is obtained. In addition, 3 in FIG.
Reference numerals 1, 41 and 51 are external electrodes of the chip-type capacitors 3 and 4 and the resistor 5, respectively, and 52 is a resistance pattern provided on the surface of the ceramic substrate.
この場合、上記グリーンシート２１Ｇ〜２６Ｇ等のグリ
ーンシートとしては、例えば、「エレクトロニク・セラ
ミクス」′８５ ３月号 頁１８〜１９に開示されてい
るような、Al2O3、CaO、SiO2、MgO、B2O3と微量添加物
から成るセラミック粉末とバインダーとを混合してドク
ターブレード法によってシート状にされたようなものが
利用される。そのようなグリーンシートは、例えば窒素
等の還元雰囲気中で焼成しても特性劣化が無く、しかも
例えば９００〜１０００℃程度の比較的低温で焼成する
ことができる。In this case, examples of the green sheets such as the above-mentioned green sheets 21G to 26G include Al 2 O 3 , CaO and SiO 2 as disclosed in "Electronic Ceramics"'85 March issue, pages 18 to 19. , A powder obtained by mixing a ceramic powder consisting of MgO, B 2 O 3 and a trace amount of additive with a binder and forming a sheet by a doctor blade method is used. Such a green sheet does not deteriorate in characteristics even when fired in a reducing atmosphere such as nitrogen, and can be fired at a relatively low temperature of, for example, about 900 to 1000 ° C.
また上記コンデンサ３、４等のコンデンサとしては、例
えば、特公昭５６−４６６４１号公報、特公昭５７
−４２５８８号公報、特公昭５７−４９５１５号公報
に開示されているようなチタン酸バリウム系の非還元性
誘電体セラミック組成物、あるいは特公昭５７−３７
０８１号公報、特公昭５７−３９００１号公報に開示
されているようなジルコン酸カルシウムを主体とする非
還元性誘電体セラミック組成物を用いた例えば積層タイ
プのセラミックコンデンサが利用できる。そのようなセ
ラミック積層コンデンサの製法の一例が上記〜の公
報中に開示されている。このようなコンデンサを用いれ
ば、グリーンシート中に収納して還元雰囲気中で焼成し
ても特性劣化を生じることがない。Examples of the capacitors such as the capacitors 3 and 4 are, for example, Japanese Patent Publication No. 56-46641 and Japanese Patent Publication No. 57.
-42588 and Japanese Patent Publication No. 57-49515, a barium titanate-based non-reducing dielectric ceramic composition, or Japanese Patent Publication No. 57-37.
For example, a multilayer type ceramic capacitor using a non-reducing dielectric ceramic composition mainly composed of calcium zirconate as disclosed in JP-B-0881 and JP-B-57-39001 can be used. An example of a method for manufacturing such a ceramic multilayer capacitor is disclosed in the above-mentioned publications. If such a capacitor is used, the characteristics will not be deteriorated even if it is housed in a green sheet and fired in a reducing atmosphere.
上記抵抗器５等の抵抗器としては、例えば、特開昭５５
−２７７００号公報、特開昭５５−２９１９９号公報に
開示されているようなランタンホウ素、イットリウムホ
ウ素等の抵抗物質と非還元性ガラスとから成る非還元性
抵抗組成物を、例えばセラミック基板上に付与して還元
雰囲気中で焼成した抵抗器が利用できる。このような抵
抗器を用いれば、グリーンシート中に収納して還元雰囲
気中で焼成しても特性劣化を生じることがない。Examples of resistors such as the resistor 5 described above are disclosed in JP-A-55
A non-reducing resistance composition comprising a resistance substance such as lanthanum boron and yttrium boron and a non-reducing glass as disclosed in JP-A-27700 and JP-A-55-29199 is provided on, for example, a ceramic substrate. A resistor applied and fired in a reducing atmosphere can be used. If such a resistor is used, characteristic deterioration does not occur even if the resistor is housed in a green sheet and fired in a reducing atmosphere.
上記導電ペースト６Ｐ等の導電ペーストとしては、グリ
ーンシートが９００〜１０００℃の還元雰囲気中で焼成
可能なため、例えばＣｕ、Ｎｉ、Ｆｅ等の卑金属から成
るものが利用できる。As the conductive paste such as the conductive paste 6P, a green sheet can be fired in a reducing atmosphere at 900 to 1000 ° C., and therefore, a base metal such as Cu, Ni, or Fe can be used.
より具体例を示すと、厚さ２００μｍのSiO2、Al2O3、B
aO、B2O3及びバインダーより成る低温焼結セラミックグ
リーンシートに、第３図に示すように貫通孔を開け、Ba
TiO3 を主成分とする非還元性積層セラミックコンデン
サ及びLa3B2を主成分とする非還元性抵抗器を貫通孔に
挿入し、またＣｕ系導電ペーストをスクリーン印刷法で
所定パターンに印刷した後、グリーンシートを圧着し、
窒素雰囲気中９５０℃で焼成して第１図に示すような電
子部品内蔵多層セラミック基板を得た。そして焼成後の
容量、抵抗をＬＣＲメータで測定したところ、設計値通
りの値が得られた。As a more specific example, SiO 2 , Al 2 O 3 , and B having a thickness of 200 μm
As shown in Fig. 3, a through-hole is opened in a low temperature sintered ceramic green sheet consisting of aO, B 2 O 3 and a binder, and Ba
A non-reducing multilayer ceramic capacitor containing TiO 3 as a main component and a non-reducing resistor containing La 3 B 2 as a main component were inserted into the through holes, and a Cu-based conductive paste was printed in a predetermined pattern by a screen printing method. After that, crimp the green sheet,
It was fired at 950 ° C. in a nitrogen atmosphere to obtain a multilayer ceramic substrate with a built-in electronic component as shown in FIG. When the capacitance and resistance after firing were measured with an LCR meter, the values as designed were obtained.
尚、第１図等に示した電子部品内蔵多層セラミック基板
はあくまでも一例であって、この発明がそのような構造
のものに限定されないことは勿論である。The multilayer ceramic substrate with a built-in electronic component shown in FIG. 1 and the like is merely an example, and it goes without saying that the present invention is not limited to such a structure.
以上のようにこの発明は、チップ形電子部品を多層セラ
ミック基板内の空間に収納した構造であるため、次のよ
うな利点がある。従来のように圧着・焼成過程で電子
部品の特性のばらつきが起きることはなく、設計値通り
の特性の電子部品を３次元的に内蔵した多層セラミック
基板が得られる。コンデンサとしても、チップ形積層
セラミックコンデンサを使用することができるので、大
きな静電容量のものが内蔵可能である。電子部品は多
層セラミック基板内に形成された空間内に収納されてい
るため、多層基板の平面性を何等悪化させることはな
く、従って積層数の大きな積層基板が容易に得られる。
電子部品は多層セラミック基板内に実装されているた
め、耐湿性等の耐環境性が良く、従って信頼性の高い製
品が得られる。As described above, the present invention has the following advantages because it has a structure in which the chip type electronic component is housed in the space inside the multilayer ceramic substrate. There is no variation in the characteristics of the electronic components during the pressure bonding and firing process as in the past, and a multilayer ceramic substrate in which electronic components having the characteristics as designed are three-dimensionally embedded can be obtained. Since a chip-type monolithic ceramic capacitor can be used as the capacitor, a capacitor having a large capacitance can be built in. Since the electronic component is housed in the space formed in the multilayer ceramic substrate, the flatness of the multilayer substrate is not deteriorated at all, and thus a laminated substrate having a large number of laminated layers can be easily obtained.
Since the electronic components are mounted in the multilayer ceramic substrate, environmental resistance such as humidity resistance is good, and therefore a highly reliable product can be obtained.
しかもこの発明は、多層セラミック基板が非還元性のセ
ラミックから成ること、内蔵のチップ形電子部品が非還
元性のものであること、およびチップ形電子部品を配線
している導体が卑金属から成ることを特徴としており、
これにより、多層セラミック基板をその内部に予め完成
したチップ形電子部品を収納した状態で一体的に形成し
てもチップ形電子部品の特性劣化が発生せず、しかもチ
ップ形電子部品の内蔵と共に導体によるチップ形電子部
品の配線も同時に行うことができるという効果に加え
て、導体に卑金属を用いているので、貴金属を用いた場
合に比べてコスト的にも安くできるという効果も得られ
る。Moreover, the present invention is such that the multilayer ceramic substrate is made of non-reducing ceramic, the built-in chip electronic component is non-reducing, and the conductor for wiring the chip electronic component is made of base metal. Is characterized by
As a result, even if the multilayer ceramic substrate is integrally formed in a state where the completed chip-type electronic component is housed inside, the characteristic deterioration of the chip-type electronic component does not occur, and moreover, the built-in chip-type electronic component and the conductor are integrated. In addition to the effect that the wiring of the chip type electronic component can be performed at the same time, the effect that the cost can be reduced as compared with the case of using the noble metal because the base metal is used for the conductor is also obtained.
第１図はこの発明の一実施例に係る電子部品内蔵多層セ
ラミック基板を示す概略断面図であり、第２図はその等
価回路図である。第３図は、第１図の電子部品内蔵多層
セラミック基板の組み立て前の状態を示す概略断面図で
ある。 ２……多層セラミック基板、２１〜２６……セラミック
基板、２１Ｇ〜２６Ｇ……グリーンシート、３，４……
コンデンサ、５……抵抗器、６……導体、７……貫通孔FIG. 1 is a schematic sectional view showing a multilayer ceramic substrate with a built-in electronic component according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. FIG. 3 is a schematic cross-sectional view showing a state before assembly of the electronic component-embedded multilayer ceramic substrate of FIG. 1. 2 ... Multilayer ceramic substrate, 21-26 ... Ceramic substrate, 21G-26G ... Green sheet, 3, 4 ...
Capacitor, 5 ... Resistor, 6 ... Conductor, 7 ... Through hole
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鷹木 洋 京都府長岡京市天神２丁目26番10号 株式 会社村田製作所内 (56)参考文献 特開 昭60−109296（ＪＰ，Ａ) 特開 昭57−4192（ＪＰ，Ａ) 特開 昭59−84493（ＪＰ，Ａ) 特開 昭57−154886（ＪＰ，Ａ) 特開 昭57−154862（ＪＰ，Ａ) 実開 昭59−9568（ＪＰ，Ｕ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroshi Takagi 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Murata Manufacturing Co., Ltd. (56) Reference JP-A-60-109296 (JP, A) JP-A-57 -4192 (JP, A) JP 59-84493 (JP, A) JP 57-154886 (JP, A) JP 57-154862 (JP, A) Actual development 59-9568 (JP, U) )
Claims (1)
を含む複数枚のセラミック基板であっていずれも非還元
性のセラミックから成るものが一体的に焼成積層されて
成る多層セラミック基板と、この多層セラミック基板内
であって前記凹部または貫通孔で形成される空間内に収
納された非還元性のチップ形電子部品と、前記多層セラ
ミック基板の層間または前記貫通孔内に設けられていて
前記チップ形電子部品を配線している卑金属から成る導
体とを備えることを特徴とする電子部品内蔵多層セラミ
ック基板。1. A multilayer ceramic substrate comprising a plurality of ceramic substrates including a ceramic substrate having a recess or a through hole, each of which is made of non-reducing ceramic and integrally fired and laminated, and the multilayer ceramic substrate. A non-reducing chip-type electronic component housed in a space formed by the recess or the through hole in the substrate, and the chip-type electronic component provided between the layers of the multilayer ceramic substrate or in the through hole A multilayer ceramic substrate with a built-in electronic component, comprising: a conductor made of a base metal for wiring components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60130647A JPH0632378B2 (en) | 1985-06-14 | 1985-06-14 | Multi-layer ceramic board with built-in electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60130647A JPH0632378B2 (en) | 1985-06-14 | 1985-06-14 | Multi-layer ceramic board with built-in electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61288498A JPS61288498A (en) | 1986-12-18 |
| JPH0632378B2 true JPH0632378B2 (en) | 1994-04-27 |
Family
ID=15039252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60130647A Expired - Lifetime JPH0632378B2 (en) | 1985-06-14 | 1985-06-14 | Multi-layer ceramic board with built-in electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0632378B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7417196B2 (en) | 2004-09-13 | 2008-08-26 | Murata Manufacturing Co., Ltd. | Multilayer board with built-in chip-type electronic component and manufacturing method thereof |
| US7655103B2 (en) | 2004-10-29 | 2010-02-02 | Murata Manufacturing Co., Ltd. | Ceramic multilayer substrate and method for manufacturing the same |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274099A (en) * | 1988-09-09 | 1990-03-14 | Murata Mfg Co Ltd | Electronic component built-in multilayer resin board |
| US5055966A (en) * | 1990-12-17 | 1991-10-08 | Hughes Aircraft Company | Via capacitors within multi-layer, 3 dimensional structures/substrates |
| US5164699A (en) * | 1990-12-17 | 1992-11-17 | Hughes Aircraft Company | Via resistors within-multi-layer, 3 dimensional structures substrates |
| JP3322199B2 (en) * | 1998-01-06 | 2002-09-09 | 株式会社村田製作所 | Multilayer ceramic substrate and method of manufacturing the same |
| JP4012652B2 (en) * | 1999-07-22 | 2007-11-21 | 京セラ株式会社 | Semiconductor device |
| US7488895B2 (en) | 2003-09-29 | 2009-02-10 | Panasonic Corporation | Method for manufacturing component built-in module, and component built-in module |
| JP2005197800A (en) * | 2003-12-26 | 2005-07-21 | Kyocera Kinseki Corp | Piezoelectric component and manufacturing method thereof |
| US7750247B2 (en) | 2004-10-29 | 2010-07-06 | Murata Manufacturing Co., Ltd. | Multilayer substrate with built-in-chip-type electronic component and method for manufacturing the same |
| JP5293605B2 (en) | 2007-09-10 | 2013-09-18 | 株式会社村田製作所 | Ceramic multilayer substrate and manufacturing method thereof |
| JP4841650B2 (en) * | 2009-06-22 | 2011-12-21 | 京セラ株式会社 | Manufacturing method of wiring board with built-in electric element |
| US8500252B2 (en) * | 2010-11-05 | 2013-08-06 | Canon Kabushiki Kaisha | Liquid ejection head and method of manufacturing the same |
| DE102016108604A1 (en) * | 2016-05-10 | 2017-11-16 | Epcos Ag | Multi-layer component and method for producing a multilayer component |
| DE102018102144A1 (en) * | 2018-01-31 | 2019-08-01 | Tdk Electronics Ag | Electronic component |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574192A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Wiring mountng board for electronic part |
| JPS57154886A (en) * | 1981-03-19 | 1982-09-24 | Matsushita Electric Ind Co Ltd | Wiring circuit device |
| JPS57154862A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Structure for semiconductor sealing |
| JPS599568U (en) * | 1982-07-09 | 1984-01-21 | 日本電気株式会社 | Electronic component mounting structure |
| JPS5984493A (en) * | 1982-11-04 | 1984-05-16 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPS60109296A (en) * | 1983-11-17 | 1985-06-14 | 三洋電機株式会社 | Method of connecting printed circuit board |
-
1985
- 1985-06-14 JP JP60130647A patent/JPH0632378B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7417196B2 (en) | 2004-09-13 | 2008-08-26 | Murata Manufacturing Co., Ltd. | Multilayer board with built-in chip-type electronic component and manufacturing method thereof |
| US7655103B2 (en) | 2004-10-29 | 2010-02-02 | Murata Manufacturing Co., Ltd. | Ceramic multilayer substrate and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61288498A (en) | 1986-12-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |