JP2700920B2 - Composite circuit board with built-in capacitor - Google Patents

Composite circuit board with built-in capacitor

Info

Publication number
JP2700920B2
JP2700920B2 JP1127472A JP12747289A JP2700920B2 JP 2700920 B2 JP2700920 B2 JP 2700920B2 JP 1127472 A JP1127472 A JP 1127472A JP 12747289 A JP12747289 A JP 12747289A JP 2700920 B2 JP2700920 B2 JP 2700920B2
Authority
JP
Japan
Prior art keywords
capacitor
circuit board
built
composite circuit
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1127472A
Other languages
Japanese (ja)
Other versions
JPH02305490A (en
Inventor
克彦 鬼塚
晃 橋本
昭哉 藤崎
芳博 藤岡
正和 安井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
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Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1127472A priority Critical patent/JP2700920B2/en
Publication of JPH02305490A publication Critical patent/JPH02305490A/en
Application granted granted Critical
Publication of JP2700920B2 publication Critical patent/JP2700920B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、コンデンサー、抵抗体及び電気配線用導体
層を有するコンデンサー内蔵複合回路基板に関し、とり
わけ絶縁基体及び誘電体を同時に焼成して成るコンデン
サー内蔵複合回路基板に関するものである。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite circuit board with a built-in capacitor having a capacitor, a resistor and a conductor layer for electric wiring, and more particularly to a capacitor formed by simultaneously firing an insulating base and a dielectric. The present invention relates to a built-in composite circuit board.

〔従来の技術〕[Conventional technology]

近年、各種の電子部品はIC及びLSI等の半導体集積回
路素子の利用で小型化・高密度実装化が急速に進めら
れ、それに伴い前記半導体集積回路素子等を搭載する絶
縁基板も小型化とともにより高密度化が要求されてき
た。そこで、前記配線の微細化や多層化による高密度化
および電子回路におけるコンデンサーや抵抗等の受動部
品のチップ化が進められ、更にそれら小型化された受動
部品を絶縁基板の両面に設けられた電気配線用導体層に
接続した両面実装化が実用化されてきた。
In recent years, the use of semiconductor integrated circuit devices such as ICs and LSIs for various electronic components has rapidly progressed in miniaturization and high-density mounting, and accordingly, the insulating substrate on which the semiconductor integrated circuit devices and the like are mounted has become smaller and smaller. Higher densities have been required. Therefore, the miniaturization and multi-layering of the wiring and the increase in the density of passive components such as capacitors and resistors in electronic circuits have been promoted, and the miniaturized passive components have been provided on both sides of an insulating substrate. The double-sided mounting connected to the wiring conductor layer has been put to practical use.

しかし乍ら、半導体材料の著しい発達に伴って電子部
品は、より一層の小型化・高密度実装化が要求されるよ
うになり、前記受動部品の小型化等ではその要求を満足
することができなくなっていた。
However, with the remarkable development of semiconductor materials, further miniaturization and high-density mounting of electronic components are required, and the miniaturization of the passive components can satisfy the demand. Was gone.

そこでかかる要求に応えるべく、絶縁基体上に受動素
子であるコンデンサー部をスクリーン印刷法等により厚
膜印刷し、同様にして形成された電極層及び内部配線用
導体層とともに前記絶縁基体の焼成と同時に形成し、そ
の後、該絶縁基体面上に同様のスクリーン印刷法により
電気配線用導体層及び抵抗体層を形成し、該導体層及び
抵抗体層を焼付けてハイブリッド化することにより小型
化・高密度化せんとする複合セラミック基板が提案され
ている(特公昭和63-55795号公報参照)。
Therefore, in order to respond to such a demand, a capacitor part, which is a passive element, is printed on the insulating substrate by a thick film printing method or the like, and simultaneously with firing of the insulating substrate together with the electrode layer and the internal wiring conductor layer formed in the same manner. After that, a conductor layer and a resistor layer for electric wiring are formed on the surface of the insulating substrate by the same screen printing method, and the conductor layer and the resistor layer are baked to be hybridized, thereby reducing the size and the density. There has been proposed a composite ceramic substrate to be formed into a plastic (see Japanese Patent Publication No. 63-55795).

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかし乍ら、この従来の複合セラミック基板は、たと
えばチタン酸バリウム(BaTiO3)を主成分とするセラミ
ックスを誘電体層とし該誘電体層を機械的に強度が高く
化学的に安定で且つ絶縁性に優れたアルミナを主成分と
する絶縁基体中に内蔵させた場合、絶縁基体のアルミナ
セラミックスと誘電体層のチタン酸バリウムから成るセ
ラミックスとが接した状態で同時に焼成すると、前記セ
ラミックス同士が反応してしまい、所期の特性を有する
誘電体層が得られないという課題と、前記絶縁基体のア
ルミナから成るセラミックスと誘電体層のチタン酸バリ
ウムから成るセラミックスとの焼成温度を一致させるこ
とが難しく、その上、前記絶縁基体と誘電体層との熱膨
張差から誘電体層にクラックを生じ、コンデンサーとし
ての絶縁抵抗や絶縁破壊電圧が低下するという問題があ
った。
However, in this conventional composite ceramic substrate, for example, a ceramic mainly composed of barium titanate (BaTiO 3 ) is used as a dielectric layer, and the dielectric layer has high mechanical strength, is chemically stable, and has an insulating property. When embedded in an insulating base mainly composed of alumina excellent in alumina, when the alumina base ceramic of the insulating base and the ceramics of the dielectric layer made of barium titanate are simultaneously fired in a contact state, the ceramics react with each other. Therefore, it is difficult to match the problem that a dielectric layer having desired characteristics cannot be obtained and the firing temperature of the ceramics made of alumina for the insulating base and the ceramics made of barium titanate for the dielectric layer, In addition, cracks occur in the dielectric layer due to the difference in thermal expansion between the insulating base and the dielectric layer. Corrupted voltage is lowered.

〔発明の目的〕[Object of the invention]

本発明は上記欠点に鑑み案出されたもので、その目的
はMgO、SiO2、CaOを主成分とする高周波絶縁性に優れた
絶縁体層と高い誘電率を有するチタン酸バリウム(BaTi
O3)を主成分とする誘電体層を同時に焼成し、高い静電
容量を有するコンデンサーを内蔵した複合回路基板を提
供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and its object is to provide an insulating layer having MgO, SiO 2 , and CaO as main components and having excellent high-frequency insulating properties, and a barium titanate (BaTi) having a high dielectric constant.
It is an object of the present invention to provide a composite circuit board including a capacitor having a high capacitance by simultaneously firing a dielectric layer containing O 3 ) as a main component.

〔課題を解決するための手段〕[Means for solving the problem]

本発明に係るコンデンサー内蔵複合回路基板は、チタ
ン酸バリウム(BaTiO3)を主成分とするセラミックスを
誘電体層とし、該誘電体層の上下面に電極層を設けてコ
ンデンサー部を形成し、該コンデンサー部を絶縁体層で
挟持したコンデンサー内蔵複合回路基板において、上記
絶縁体層を第1図に示す下記A、B、C、D、Eの各点
で囲まれた範囲内のマグネシア(MgO)、シリカ(Si
O2)及びカルシア(CaO)を主成分とするセラミックス
からなり、かつ結晶相として少なくともフォルステライ
ト(Mg2SiO4)を含有することを特徴とする。但し、
X、Y、Zはそれぞれマグネシア(MaO)、シリカ(SiO
2)及びカルシア(CaO)の重量%を表わす。
The composite circuit board with a built-in capacitor according to the present invention is characterized in that a ceramic mainly composed of barium titanate (BaTiO 3 ) is used as a dielectric layer, and an electrode layer is provided on upper and lower surfaces of the dielectric layer to form a capacitor part. In a composite circuit board with a built-in capacitor in which a capacitor portion is sandwiched between insulator layers, magnesia (MgO) in a range surrounded by the following points A, B, C, D, and E shown in FIG. , Silica (Si
It is characterized by being composed of ceramics containing O 2 ) and calcia (CaO) as main components and containing at least forsterite (Mg 2 SiO 4 ) as a crystal phase. However,
X, Y and Z are magnesia (MaO) and silica (SiO
2 ) and weight% of calcia (CaO).

X Y Z A 60 36 4 B 46 50 4 C 20 50 30 D 40 30 30 E 60 30 10 また、絶縁体相がフォルステライト(Mg2SiO4)と、
モンチセライト(CaMgCiO4)またはアカーマナイト(Ca
2MgSi27)の少なくとも一種の結晶相を含有すること
が望ましい。
XYZ A 60 36 4 B 46 50 4 C 20 50 30 D 40 30 30 E 60 30 10 Further, the insulator phase is forsterite (Mg 2 SiO 4 ),
Monticerite (CaMgCiO 4 ) or akermanite (Ca
2 MgSi 2 O 7 ).

さらに、本願のコンデンサー内蔵複合回路基板は、誘
電体層と該誘電体層及び電極層とから形成されるコンデ
ンサー部を挟持した絶縁体層とを同時焼成して成るもの
である。
Furthermore, the composite circuit board with a built-in capacitor of the present application is obtained by simultaneously firing a dielectric layer and an insulating layer sandwiching a capacitor portion formed of the dielectric layer and the electrode layer.

即ち、前記絶縁体層の組成は第1図において、MgOが6
0重量%を越えると焼成温度が1360℃以上となり前記誘
電体材料と同時焼成できず、その上、MgOが析出し耐湿
性に劣る。他方、20重量%未満では焼成温度は1220℃以
下となり前記誘電体材料と同時焼成できない。
That is, the composition of the insulator layer was such that MgO was 6 in FIG.
If it exceeds 0% by weight, the sintering temperature becomes 1360 ° C. or higher, and the sintering cannot be performed simultaneously with the above-mentioned dielectric material. On the other hand, if it is less than 20% by weight, the sintering temperature becomes 1220 ° C. or less, and the sintering cannot be performed simultaneously with the dielectric material.

また、SiO2が50重量%を越えると絶縁体層の熱膨張率
が低下し、該絶縁体層と前記誘電体層との熱膨張差によ
り、該誘電体層にクラックが発生し、所期の誘電体特性
が得られない。他方、30重量%未満では焼成温度が1360
℃以上となり、前記誘電体材料と同時焼成できない。
If the content of SiO 2 exceeds 50% by weight, the coefficient of thermal expansion of the insulator layer decreases, and cracks occur in the dielectric layer due to the difference in thermal expansion between the insulator layer and the dielectric layer. Cannot be obtained. On the other hand, if it is less than 30% by weight, the firing temperature is 1360.
° C or more, and cannot be co-fired with the dielectric material.

一方、CaOが30重量%を越えるかあるいは4重量%未
満ではチタン酸バリウムから成るセラミックスとの反応
性が極めて大となり、所期の特性を有する誘電体層が得
られなくなる他、30重量%を越えるとCaSiO3またはCa2S
iO4等のカルシウムケイ酸塩が析出し耐湿性に劣る。
On the other hand, if CaO exceeds 30% by weight or less than 4% by weight, the reactivity with ceramics composed of barium titanate becomes extremely large, and a dielectric layer having desired characteristics cannot be obtained. Beyond, CaSiO 3 or Ca 2 S
Calcium silicate such as iO 4 precipitates and has poor moisture resistance.

故に、前記絶縁体層の組成は第1図のA、B、C、
D、Eの各点に囲まれた範囲内に特定される。
Therefore, the composition of the insulator layer is A, B, C,
It is specified within the range surrounded by the points D and E.

〔作用〕[Action]

コンデンサー部を挾持した絶縁体層の組成が、主成分
であるマグネシア(MgO)、シリカ(SiO2)及びカルシ
ア(CaO)を第1図に示すA、B、C、D、Eの各点に
囲まれた範囲内となる様に調整することにより、前記絶
縁体材料をチタン酸バリウム(BaTiO2)から成る誘電体
材料が焼結する1240℃乃至1340℃の焼成温度にて同時に
焼成一体化することができるとともに、焼成一体化され
た絶縁体層にはフォルステライト(Mg2SiO4)結晶相以
外に、該フォルステライト結晶相の熱膨張率と異なる熱
膨張率を有するモンチセライト(CaMgSiO4)またはアカ
ーマナイト(Ca2MgSi27)の結晶相が少なくとも1種
形成されて、前記絶縁体の熱膨張率が調整できることと
なる。
The composition of the insulator layer sandwiching the capacitor portion is such that magnesia (MgO), silica (SiO 2 ) and calcia (CaO), which are the main components, are added to the points A, B, C, D and E shown in FIG. By adjusting so as to fall within the enclosed range, the insulator material is simultaneously fired and integrated at a firing temperature of 1240 ° C. to 1340 ° C. at which a dielectric material made of barium titanate (BaTiO 2 ) is sintered. In addition to the forsterite (Mg 2 SiO 4 ) crystal phase, monsterite (CaMgSiO 4 ) having a coefficient of thermal expansion different from the coefficient of thermal expansion of the forsterite crystal phase is included in the insulator layer integrated by firing. Alternatively, at least one crystal phase of akermanite (Ca 2 MgSi 2 O 7 ) is formed, so that the coefficient of thermal expansion of the insulator can be adjusted.

〔実施例〕〔Example〕

次に本発明のコンデンサー内蔵複合回路基板を第2図
に示す実施例に基づき詳細に説明する。
Next, the composite circuit board with a built-in capacitor of the present invention will be described in detail based on the embodiment shown in FIG.

第2図は本発明のコンデンサー内蔵複合回路基板の一
実施例を示す断面図である。
FIG. 2 is a sectional view showing an embodiment of the composite circuit board with a built-in capacitor of the present invention.

図において、1は絶縁体層、2はコンデンサー部、3
は電気配線用導体で、前記コンデンサー部2は交互に積
層された誘電体層4と電極層5とから成る。
In the figure, 1 is an insulator layer, 2 is a capacitor part, 3
Is a conductor for electric wiring, and the capacitor part 2 is composed of a dielectric layer 4 and an electrode layer 5 alternately laminated.

前記絶縁体層1は、その組成が第1図に示す下記A、
B、C、D、Eの各点 X Y Z A 60 36 4 B 46 50 4 C 20 50 30 D 40 30 30 E 60 30 10 但し、X、Y、Zはそれぞれマグネシア(MgO)、シ
リカ(SiO2)及びカルシア(CaO)の重量%を表わす。
The insulator layer 1 has the following composition shown in FIG.
Each point of B, C, D and E XYZ A 6036 4 B 46 50 4 C 20 50 30 D 40 30 30 E 60 30 10 However, X, Y and Z are respectively magnesia (MgO) and silica (SiO 2 ) and weight% of calcia (CaO).

で囲まれた範囲内となるように、MgO、SiO2及びCaOから
成るセラミック原料粉末を混合し、該混合物を1100℃乃
至1300℃の温度で仮焼する。その後、前記仮焼物を粉砕
したセラミック粉末に適当な有機バインダー、分散剤、
可塑剤及び溶媒を添加混合して泥漿物を作り、該泥漿物
をたとえば従来周知のドクターブレード法等によりシー
ト状に成形し、得られたグリーンシートを複数枚積層し
たものから形成される。
The ceramic raw material powder composed of MgO, SiO 2 and CaO is mixed so as to fall within the range surrounded by, and the mixture is calcined at a temperature of 1100 ° C. to 1300 ° C. Then, an appropriate organic binder, a dispersant, and a ceramic powder obtained by pulverizing the calcined product,
A mud is formed by adding and mixing a plasticizer and a solvent, and the mud is formed into a sheet by, for example, a conventionally known doctor blade method or the like, and a plurality of obtained green sheets are laminated.

また、前記コンデンサー部2はBaTiO3を主成分とする
誘電体材料の原料粉末に適当な有機バインダー、分散
剤、可塑剤、及び溶剤を添加混合して泥漿物を作り、該
泥漿物を例えば従来周知の引き上げ法等によりシート状
に成形する。得られた誘電体のグリーンシートにはその
上面に銀・パラジウム(Ag-Pd)合金等の金属粉末に適
当な溶剤、溶媒を添加混合した合金ペーストを従来周知
のスクリーン印刷法等により所定の電極パターンに被着
し、電極層5を形成する。
Further, the condenser section 2 forms a slurry by adding and mixing an appropriate organic binder, a dispersant, a plasticizer, and a solvent to a raw material powder of a dielectric material containing BaTiO 3 as a main component. It is formed into a sheet by a known lifting method or the like. The resulting dielectric green sheet has a predetermined electrode coated on its upper surface with a metal powder such as a silver-palladium (Ag-Pd) alloy and an appropriate solvent, and an alloy paste obtained by adding a solvent thereto by a well-known screen printing method or the like. The electrode layer 5 is formed on the pattern.

尚、絶縁体層1及びコンデンサー部2の上下面の導通
をはかるため、絶縁体及び誘電体のグリーンシートには
打ち抜き加工等によりスルーホール部6が形成され、該
スルーホール部6には前記合金ペーストが充填されてい
る。
In order to conduct the upper and lower surfaces of the insulator layer 1 and the capacitor portion 2, through holes 6 are formed in the insulator and dielectric green sheets by punching or the like. Paste is filled.

次いで、前記絶縁体及び誘電体のグリーンシートを夫
々積層して熱圧着し、得られた積層体を大気中、200℃
乃至400℃の温度で脱バインダーし、その後、1240℃乃
至1340℃の温度にて一体化焼成することにより、コンデ
ンサー部2を内蔵した絶縁基板を得る。
Next, the insulator and the green sheet of the dielectric were respectively laminated and thermocompression-bonded, and the obtained laminate was exposed to air at 200 ° C.
The binder is removed at a temperature of 1 to 400 ° C., and then integrated firing is performed at a temperature of 1240 to 1340 ° C. to obtain an insulating substrate having the capacitor unit 2 built therein.

かくして前記一体焼成後の絶縁体層1表面にスクリー
ン印刷法によりAg-Pd系合金ペーストを使用して電気配
線用導体パターンを、また必要に応じて酸化ルテニウム
(RuO2)等を主成分とするペーストを使用して抵抗パタ
ーンをそれぞれ印刷形成し、大気中および850℃の温度
で焼成することにより抵抗体7を有するコンデンサー内
蔵複合回路基板が得られる。
Thus, the conductor pattern for electric wiring is formed on the surface of the insulator layer 1 after the integrally firing by using the Ag-Pd-based alloy paste by screen printing, and if necessary, ruthenium oxide (RuO 2 ) or the like as a main component. Each of the resistor patterns is printed and formed using the paste, and baked in the air and at a temperature of 850 ° C., whereby a composite circuit board with a built-in capacitor having the resistor 7 is obtained.

また、電気配線用導体パターンに銅(Cu)を主成分と
するペーストを使用する場合には、抵抗パターンに硼化
ランタン(LaB6)や酸化スズ(SnO2)を主成分とするペ
ーストを使用して印刷し、窒素雰囲気中およそ900℃の
温度で焼成することにより、前記と同様のコンデンサー
内蔵複合回路基板が得られる。
When using a paste mainly composed of copper (Cu) for the conductor pattern for electric wiring, use a paste mainly composed of lanthanum boride (LaB 6 ) or tin oxide (SnO 2 ) for the resistance pattern. By printing and firing at about 900 ° C. in a nitrogen atmosphere, a composite circuit board with a built-in capacitor similar to that described above is obtained.

次に実験例に基づき本発明を説明する。 Next, the present invention will be described based on experimental examples.

絶縁体層の組成が第1表に示す組成比となる様に、Mg
O、SiO2およびCaOから成るセラミック原料粉末を混合
し、該混合物を1100℃乃至1300℃の温度で仮焼を行っ
た。その後、前記仮焼物を所望の粒度に粉砕調整し、得
られた原料粉末に適当な有機バインダー及び溶媒を添加
して泥漿状となすとともに、該泥漿物をドクターブレー
ド法により厚さ約200μmのグリーンシートを成形し、
しかる後、該グリーンシートに打ち抜き加工を施し、17
0mm角の絶縁体シートを得た。
Mg so that the composition of the insulator layer has the composition ratio shown in Table 1.
Ceramic raw material powders composed of O, SiO 2 and CaO were mixed, and the mixture was calcined at a temperature of 1100 ° C. to 1300 ° C. Thereafter, the calcined product is pulverized and adjusted to a desired particle size, an appropriate organic binder and a solvent are added to the obtained raw material powder to form a slurry, and the slurry is greened to a thickness of about 200 μm by a doctor blade method. Form the sheet,
Thereafter, the green sheet is subjected to a punching process, and 17
A 0 mm square insulator sheet was obtained.

一方、チタン酸バリウム(BaTiO3)を主成分とするセ
ラミック原料粉末に適当な有機バインダー及び溶媒を添
加混合して泥漿状となすとともに、該泥漿物を引き上げ
法によりコンデンサーの容量設定のため厚さ20μm乃至
60μmのグリーンシートを成形し、しかる後、該グリー
ンシートに打ち抜き加工を施し、170mm角の誘電体シー
トを得た。
On the other hand, a ceramic raw material powder containing barium titanate (BaTiO 3 ) as a main component is mixed with an appropriate organic binder and a solvent to form a slurry, and the slurry is pulled up to set a thickness of a capacitor. 20 μm or more
A green sheet of 60 μm was formed, and thereafter, the green sheet was punched to obtain a 170 mm square dielectric sheet.

次いで、前記誘電体シートにスクリーン印刷等の厚膜
印刷法によりAg-Pd合金ペーストを用いて約1mm乃至10mm
角の電極パターンを必要とする静電容量に応じて印刷形
成する。
Then, about 1 mm to 10 mm using Ag-Pd alloy paste by a thick film printing method such as screen printing on the dielectric sheet.
A corner electrode pattern is printed and formed according to the required capacitance.

また、前記絶縁体シート及び誘電体シートに予め、形
成されたスルーホール部にもスクリーン印刷法等により
Ag-Pd合金ペーストを充填する。
Also, a screen printing method or the like is applied to the through holes formed in advance on the insulator sheet and the dielectric sheet.
Fill with Ag-Pd alloy paste.

しかる後、前記絶縁体シートの間にチタン酸バリウム
から成る誘電体シートを複数枚挾み込み、熱圧着し、得
られた積層体を大気中200℃乃至400℃の温度で脱バイン
ダーし、続いて第1表に示す温度にて大気中で焼成す
る。
Thereafter, a plurality of dielectric sheets made of barium titanate are sandwiched between the insulator sheets, thermocompression-bonded, and the resulting laminate is debindered at a temperature of 200 ° C. to 400 ° C. in the air. And fired in the air at the temperatures shown in Table 1.

上記評価試料によりLCRメーターを使用してコンデン
サー部の電極層間の短絡の有無を確認した後、JIS C 51
02の規定に準じて前記LCRメーターにより周波数1KHz、
入力信号レベル1.0Vrmsの測定条件にてコンデンサー部
の静電容量を測定し、該静電容量から比誘電率(εr
を算出し、一方、−55℃及び125℃における静電容量を
測定して該静電容量の変化率を温度係数(TCC)として
算出した。また、コンデンサー部の絶縁抵抗値は25Vの
直流電圧を印加し60秒後に測定した抵抗値とし、絶縁破
壊電圧はコンデンサー部の端子間に毎秒100Vの昇圧速度
で電圧を印加した時の漏れ電流値が1.0mAを越えた瞬間
の電圧値とした。
After checking the presence or absence of a short circuit between the electrode layers of the capacitor part using an LCR meter with the above evaluation sample, JIS C 51
According to the provisions of 02, the LCR meter frequency 1KHz,
The capacitance of the capacitor part is measured under the measurement condition of the input signal level 1.0 Vrms, and the relative dielectric constant (ε r ) is obtained from the capacitance.
On the other hand, the capacitance at −55 ° C. and 125 ° C. was measured, and the rate of change of the capacitance was calculated as a temperature coefficient (TCC). The insulation resistance value of the capacitor part is the resistance value measured 60 seconds after applying a 25 V DC voltage, and the insulation breakdown voltage is the leakage current value when a voltage is applied between the terminals of the capacitor part at a step-up rate of 100 V per second. Is the voltage value at the moment when the voltage exceeds 1.0 mA.

一方、絶縁体層の結晶層は、前記評価試料を使用して
X線回折測定を行い、評価試料表面のX線回折パターン
により同定した。また、絶縁体層及び誘電体層の熱膨張
率は、それぞれ前記評価試料と同一組成である縦3mm、
横3mm、長さ40mmの角柱状の試験片を前記評価試料の焼
成と同時に焼成し、40℃乃至800℃の温度範囲における
平均熱膨張率を測定した。
On the other hand, the crystal layer of the insulator layer was subjected to X-ray diffraction measurement using the evaluation sample, and identified by an X-ray diffraction pattern on the surface of the evaluation sample. The thermal expansion coefficients of the insulator layer and the dielectric layer were 3 mm in length, each having the same composition as the evaluation sample,
A prism-shaped test piece having a width of 3 mm and a length of 40 mm was fired simultaneously with the firing of the evaluation sample, and an average coefficient of thermal expansion in a temperature range of 40 ° C. to 800 ° C. was measured.

以上の結果を第1表に示す。 Table 1 shows the above results.

〔発明の効果〕 本発明のコンデンサー内蔵複合回路基板によれば、マ
グネシア、シリカ及びカルシアを主成分とする高周波絶
縁性に優れた絶縁体層と高い誘電率を有するチタン酸バ
リウムを主成分とする誘電体材料とが互いに反応するこ
となく同時に焼成一体化することができる上、前記絶縁
体層と誘電体層の熱膨張率を互いに極めて近似したもの
とすることができることから、誘電体層にクラック等の
欠陥を生じることなく絶縁抵抗及び絶縁破壊電圧に優れ
た高い静電容量を有するコンデンサー部を内蔵すること
が可能となり、その結果、ハイブリッド基板等に最適な
小型化・高密度化されたコンデンサー内蔵複合回路基板
を得ることができる。
[Effects of the Invention] According to the composite circuit board with a built-in capacitor of the present invention, an insulator layer having excellent high-frequency insulation properties mainly composed of magnesia, silica and calcia and a barium titanate having a high dielectric constant are mainly composed. Since the dielectric material and the dielectric material can be fired and integrated at the same time without reacting with each other, and the thermal expansion coefficients of the insulating layer and the dielectric layer can be made very close to each other, cracks may be formed on the dielectric layer. It is possible to incorporate a capacitor part with high capacitance excellent in insulation resistance and breakdown voltage without causing defects such as defects, and as a result, a miniaturized and high-density capacitor optimal for hybrid substrates etc. A built-in composite circuit board can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の絶縁体層の組成範囲を示す三元系図、
第2図は本発明のコンデンサー内蔵複合回路基板の一実
施例を示す断面図である。 1……絶縁体層 2……コンデンサー部 4……誘電体層 5……電極層
FIG. 1 is a ternary diagram showing the composition range of the insulator layer of the present invention,
FIG. 2 is a sectional view showing an embodiment of the composite circuit board with a built-in capacitor of the present invention. DESCRIPTION OF SYMBOLS 1 ... Insulator layer 2 ... Capacitor part 4 ... Dielectric layer 5 ... Electrode layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 安井 正和 鹿児島県国分市山下町1番1号 京セラ 株式会社鹿児島国分工場内 審査官 松本 貢 (56)参考文献 特開 昭58−17651(JP,A) 特開 昭63−295473(JP,A) 特開 昭62−265795(JP,A) 特開 平1−95591(JP,A) ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masakazu Yasui 1-1, Yamashita-cho, Kokubu-shi, Kagoshima Kyocera Inspector in Kagoshima Kokubu Plant Mitsuru Matsumoto (56) References JP-A-58-17651 (JP, A JP-A-63-295473 (JP, A) JP-A-62-265795 (JP, A) JP-A-1-95591 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】チタン酸バリウム(BaTiO3)を主成分とす
るセラミックスを誘電体層とし、該誘電体層の上下面に
電極層を設けてコンデンサー部を形成し、該コンデンサ
ー部を絶縁体層で挟持したコンデンサー内蔵複合回路基
板において、上記絶縁体層が第1図に示す下記A、B、
C、D、Eの各点で囲まれた範囲内のマグネシア(Mg
O)、シリカ(SiO2)及びカルシア(CaO)を主成分とす
るセラミックスからなり、かつ結晶相として少なくとも
フォルステライト(Mg2SiO4)を含有することを特徴と
するコンデンサー内蔵複合回路基板。但し、X、Y、Z
はそれぞれマグネシア(MgO)、シリカ(SiO2)及びカ
ルシア(CaO)の重量%を表わす。 X Y Z A 60 36 4 B 46 50 4 C 20 50 30 D 40 30 30 E 60 30 10
1. A capacitor part is formed by using ceramics containing barium titanate (BaTiO 3 ) as a main component as a dielectric layer, and providing electrode layers on upper and lower surfaces of the dielectric layer to form a capacitor part. In the composite circuit board with a built-in capacitor sandwiched between the above, the above-mentioned insulator layer has the following A, B, shown in FIG.
Magnesia (Mg) within the range surrounded by each point of C, D, and E
O), a composite circuit board with a built-in capacitor, comprising ceramics containing silica (SiO 2 ) and calcia (CaO) as main components and containing at least forsterite (Mg 2 SiO 4 ) as a crystal phase. Where X, Y, Z
Represents the weight percentage of magnesia (MgO), silica (SiO 2 ) and calcia (CaO), respectively. XYZ A 60 36 4 B 46 50 4 C 20 50 30 D 40 30 30 E 60 30 10
【請求項2】前記絶縁体層がフォルステライト(Mg2SiO
4)と、モンチセライト(CaMgSiO4)またはアカーマナ
イト(Ca2MgSi27)の少なくとも一種の結晶相を含有
することを特徴とする特許請求の範囲第1項記載のコン
デンサー内蔵複合回路基板。
2. The method according to claim 1, wherein said insulator layer is forsterite (Mg 2 SiO 2).
4. The composite circuit board with a built-in capacitor according to claim 1, wherein said composite circuit board contains at least one crystal phase of monticerite (CaMgSiO 4 ) or akermanite (Ca 2 MgSi 2 O 7 ).
【請求項3】前記誘電体層と該誘電体層及び電極層とか
ら形成されるコンデンサー部を挟持した絶縁体層とを同
時焼成して成ることを特徴とする特許請求の範囲第1項
記載のコンデンサー内蔵複合回路基板。
3. The method according to claim 1, wherein said dielectric layer and an insulator layer sandwiching a capacitor portion formed of said dielectric layer and said electrode layer are simultaneously fired. Composite circuit board with built-in capacitor.
JP1127472A 1989-05-19 1989-05-19 Composite circuit board with built-in capacitor Expired - Fee Related JP2700920B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1127472A JP2700920B2 (en) 1989-05-19 1989-05-19 Composite circuit board with built-in capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1127472A JP2700920B2 (en) 1989-05-19 1989-05-19 Composite circuit board with built-in capacitor

Publications (2)

Publication Number Publication Date
JPH02305490A JPH02305490A (en) 1990-12-19
JP2700920B2 true JP2700920B2 (en) 1998-01-21

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ID=14960772

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Application Number Title Priority Date Filing Date
JP1127472A Expired - Fee Related JP2700920B2 (en) 1989-05-19 1989-05-19 Composite circuit board with built-in capacitor

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Country Link
JP (1) JP2700920B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525921B1 (en) 1999-11-12 2003-02-25 Matsushita Electric Industrial Co., Ltd Capacitor-mounted metal foil and a method for producing the same, and a circuit board and a method for producing the same
KR100956219B1 (en) * 2008-02-25 2010-05-04 삼성전기주식회사 Low Temperature Co-fired Ceramics with diffusion-blocking layer and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5817651A (en) * 1981-07-24 1983-02-01 Hitachi Ltd Multilayer circuit board and its manufacture
JPS62265795A (en) * 1986-05-14 1987-11-18 株式会社住友金属セラミックス Ceramic board with built-in capacitor
JPS63295473A (en) * 1987-05-27 1988-12-01 Shoei Kagaku Kogyo Kk Dielectric material for circuit board
JP2555638B2 (en) * 1987-10-07 1996-11-20 株式会社村田製作所 Method for manufacturing multilayer ceramic substrate

Also Published As

Publication number Publication date
JPH02305490A (en) 1990-12-19

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