JPS5910585B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5910585B2 JPS5910585B2 JP206279A JP206279A JPS5910585B2 JP S5910585 B2 JPS5910585 B2 JP S5910585B2 JP 206279 A JP206279 A JP 206279A JP 206279 A JP206279 A JP 206279A JP S5910585 B2 JPS5910585 B2 JP S5910585B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- resin
- bonded
- electrode lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【発明の詳細な説明】
本発明は、半導体素子の電極端子に重ね合わせできる様
にパターニングされた電極端子を有するパッケージ基板
に半導体素子が組立てられた半導体装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor element is assembled on a package substrate having electrode terminals patterned so as to overlap electrode terminals of the semiconductor element.
近年、従来のセラミックや金属フレームでできたパッケ
ージに半導体素子を接合し、その電極端子と前記パッケ
ージの所定の電極端子とをAl、Au等の細線でワイヤ
ボンディングする方法にかわつて、Cu等の可撓性金属
箔からなりー部が半導体素子の電極端子に重ね合わせで
きる様にパターニングされた細条の電極リードを有する
パッケージ基板(以下キャリアテープと呼ぶ)を用い、
前記半導体素子の複数の電極端子を同時にキャリアテー
プの電極リードに接合する方法が多く用いられて来た。In recent years, instead of the conventional method of bonding a semiconductor element to a package made of ceramic or metal frame and wire-bonding its electrode terminal to a predetermined electrode terminal of the package with a thin wire of Al, Au, etc. Using a package substrate (hereinafter referred to as carrier tape) made of flexible metal foil and having thin strip electrode leads patterned so that the portion can be overlapped with the electrode terminal of the semiconductor element,
Many methods have been used to simultaneously bond a plurality of electrode terminals of the semiconductor element to electrode leads of a carrier tape.
ところがこの方法では半導体素子の裏面がパッケージに
接着されていないため半導体素子から発生した熱を放散
する特性が極めて悪い等の欠点があり、その対策方法と
しては第1図にその一例を示す様にキャリアテープ2に
半導体素子1を結合した後、半導体素子裏面に金属板3
を接着し、樹脂5等により半導体素子を封止後前記金属
板3に放熱体を成す放熱フィン6を取りつける方法が用
いられている。However, this method has drawbacks such as extremely poor ability to dissipate heat generated from the semiconductor element because the back side of the semiconductor element is not bonded to the package. After bonding the semiconductor element 1 to the carrier tape 2, a metal plate 3 is attached to the back side of the semiconductor element.
A method is used in which a heat dissipating fin 6 serving as a heat dissipating body is attached to the metal plate 3 after the semiconductor element is sealed with a resin 5 or the like.
この従来の方法の製造工程を第2図a−cに示す。The manufacturing steps of this conventional method are shown in FIGS. 2a-c.
第2図aはキャリアテープ2の電極リード2−aに半導
体素子1が電気的機械的に接合され” た状態を示す。
図中2−bはキャリアテープ2の電極リード2−aを支
持する目的の絶縁フィルムである。第2図bは第2図a
で示した半導体素子1の裏面に半田、接着樹脂等4によ
りCu、Mo、コバール(Kovar)等で形成された
板3を接着し・ た状態を示す。第2図cは第2図bで
示した半導体素子1、及び電極リード2−aと半導体素
子1の接合部分を、外気からエポキシ、シリコン等の樹
脂5で封止した状態を示す。この様に樹脂5で封止した
後、金属板3に樹脂、半田等7により放O 熱フィン6
をつけて完成する。ところがこの従来の方法においては
、電極リード2−aに接合された半導体素子1の裏面に
金属板3を接着する際のストレス等により、電極リード
2−aと半導体素子1の接合箇所の破壊を引き5 起こ
すことが起りうる。FIG. 2a shows a state in which the semiconductor element 1 is electrically and mechanically bonded to the electrode lead 2-a of the carrier tape 2.
In the figure, 2-b is an insulating film for supporting the electrode lead 2-a of the carrier tape 2. Figure 2b is Figure 2a
This figure shows a state in which a plate 3 made of Cu, Mo, Kovar, etc. is bonded to the back surface of the semiconductor element 1 shown in FIG. FIG. 2c shows a state in which the semiconductor element 1 shown in FIG. 2b and the joint portion between the electrode lead 2-a and the semiconductor element 1 are sealed from the outside air with a resin 5 such as epoxy or silicon. After sealing with resin 5 in this way, O is released onto metal plate 3 with resin, solder, etc. 7 Heat fin 6
Add and complete. However, in this conventional method, the bonding portion between the electrode lead 2-a and the semiconductor element 1 may be damaged due to stress, etc. when bonding the metal plate 3 to the back surface of the semiconductor element 1 bonded to the electrode lead 2-a. Trigger 5 Something can happen.
又、半導体素子1と放熱フィン6の間に接着層と金属層
が存在するため熱抵抗の増大をもたらす等の欠点を有す
る。本発明は斯る欠点を改良するものである。Furthermore, since there is an adhesive layer and a metal layer between the semiconductor element 1 and the heat dissipating fin 6, there are drawbacks such as an increase in thermal resistance. The present invention aims to improve these drawbacks.
以下、実施例について説明する。第3図は本発明の一実
施例を示す断面図である〇図中、8はセラミツク、樹脂
、表面を絶縁処理した金属、等による板状のキヤツプで
ある。Examples will be described below. FIG. 3 is a sectional view showing an embodiment of the present invention. In the figure, 8 is a plate-shaped cap made of ceramic, resin, metal whose surface has been insulated, or the like.
又、放熱フイン6は半田、接着剤等4により半導体素子
1の裏面に直づけされている。第4図A,bにその製造
工程を示す。第4図aは第2図aに示した状態に於て、
キヤツブ8をエポキシ、シリコン等の樹脂5−aで半導
体素子1の電極リード2−aとの接合表面上に接着した
状態を示す。第4図bは第4図aに示した半導体素子1
の裏面に半田、接着剤等4により放熱フイン6を接着し
た状態を示す。この状態で半導体素子1の露出部分を樹
脂5で封止することにより半導体装置が出来上る。以上
かられかる如く、本発明によると、半導体素子1と電極
リード2−aを接合後キヤツプ8を接着して、半導体素
子1と電極リード2−aの接合部分を固着することによ
り、半導体素子1の裏面の放熱フイン6をつける際のス
トレスによる前 ≧記接合部分の破壊を防ぎ、かつ半導
体素子1に直接放熱フイン6を接着するため熱抵抗を低
くできる。さらに、半導体装置の表面キヤツプ8により
平坦にすれば半導体装置の実装も従来の装置の表面が丸
いものよりし易い等の長所を有するが、本発明において
、キヤツブの形状、材質、放熱フインの形状、材質、放
熱フインを接着する接着層の材質、封止樹脂の材質等は
何ら制限をうけるものではない。Further, the heat radiation fins 6 are directly attached to the back surface of the semiconductor element 1 using solder, adhesive, or the like 4. The manufacturing process is shown in FIGS. 4A and 4B. Figure 4a shows the state shown in Figure 2a,
A state in which the cap 8 is bonded to the surface of the semiconductor element 1 to be bonded to the electrode lead 2-a with a resin 5-a such as epoxy or silicone is shown. FIG. 4b shows the semiconductor device 1 shown in FIG. 4a.
A heat dissipating fin 6 is shown bonded to the back surface of the device using solder, adhesive, etc. 4. In this state, the exposed portion of the semiconductor element 1 is sealed with resin 5 to complete a semiconductor device. As can be seen from the above, according to the present invention, after bonding the semiconductor element 1 and the electrode lead 2-a, the cap 8 is bonded to fix the bonded portion of the semiconductor element 1 and the electrode lead 2-a, thereby making it possible to bond the semiconductor element 1 and the electrode lead 2-a. This prevents damage to the bonded portion due to stress when attaching the heat dissipation fins 6 on the back side of the semiconductor element 1, and also lowers thermal resistance because the heat dissipation fins 6 are bonded directly to the semiconductor element 1. Furthermore, if the surface of the semiconductor device is made flat by the cap 8, it is easier to mount the semiconductor device than the conventional device with a round surface. , the material, the material of the adhesive layer to which the heat dissipation fin is bonded, the material of the sealing resin, etc. are not subject to any restrictions.
第1図は従来の半導体装置の断面図、第2図Ab,Cは
第1図の半導体装置の製造工程を示す断面図、第3図は
本発明の一実施例の半導体装置の断面図、第4図A,b
は第3図半導体装置の製造工程を示す断面図である。
図中、1は半導体素子、2はパツケージ基板(キヤリア
テープ),2−aは電極リード、2−bは絶縁フイルム
、4は半田、接着樹脂等、5,5一aは封止樹脂、6は
放熱体(放熱フイン),8はキヤツブを示す。FIG. 1 is a sectional view of a conventional semiconductor device, FIGS. 2A and 2C are sectional views showing the manufacturing process of the semiconductor device of FIG. 1, and FIG. 3 is a sectional view of a semiconductor device according to an embodiment of the present invention. Figure 4 A, b
FIG. 3 is a sectional view showing the manufacturing process of the semiconductor device. In the figure, 1 is a semiconductor element, 2 is a package substrate (carrier tape), 2-a is an electrode lead, 2-b is an insulating film, 4 is solder, adhesive resin, etc., 5, 5a is a sealing resin, 6 8 indicates a heat dissipation body (heat dissipation fin) and a cap.
Claims (1)
できる様にパターニングされた金属細条よりなる電極リ
ードを有するパッケージ基板と、このパッケージ基板の
電極リードの所定の位置に電気的機械的に接合された半
導体素子と、前記パッケージ基板の半導体素子接続側と
反対面に接着されたキャップと、前記半導体素子の裏面
に直接接着された放熱体と、前記半導体素子を外気から
封止する樹脂を備えたことを特徴とする半導体装置。 2 放熱体は、半導体素子に接着される部分のみ平坦で
他の部分には放熱効果を高めるフィンが形成されたこと
を特徴とする半導体装置。[Scope of Claims] 1. A package substrate having an electrode lead made of a metal strip patterned so that a portion thereof can be overlapped with the electrode terminal of a semiconductor element, and a predetermined position of the electrode lead of this package substrate. a semiconductor element electrically and mechanically bonded to the semiconductor element; a cap adhered to the opposite side of the package substrate to the side to which the semiconductor element is connected; a heat sink directly adhered to the back side of the semiconductor element; 1. A semiconductor device characterized by comprising a resin that is sealed with a resin. 2. A semiconductor device characterized in that the heat dissipation body is flat only in the part bonded to the semiconductor element and has fins formed in other parts to enhance the heat dissipation effect.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP206279A JPS5910585B2 (en) | 1979-01-10 | 1979-01-10 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP206279A JPS5910585B2 (en) | 1979-01-10 | 1979-01-10 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5595348A JPS5595348A (en) | 1980-07-19 |
JPS5910585B2 true JPS5910585B2 (en) | 1984-03-09 |
Family
ID=11518848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP206279A Expired JPS5910585B2 (en) | 1979-01-10 | 1979-01-10 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5910585B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5760465A (en) * | 1996-02-01 | 1998-06-02 | International Business Machines Corporation | Electronic package with strain relief means |
-
1979
- 1979-01-10 JP JP206279A patent/JPS5910585B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5595348A (en) | 1980-07-19 |
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