JPS59101928A - デ−タ解読装置 - Google Patents
デ−タ解読装置Info
- Publication number
- JPS59101928A JPS59101928A JP57210778A JP21077882A JPS59101928A JP S59101928 A JPS59101928 A JP S59101928A JP 57210778 A JP57210778 A JP 57210778A JP 21077882 A JP21077882 A JP 21077882A JP S59101928 A JPS59101928 A JP S59101928A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- output
- index
- binary data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57210778A JPS59101928A (ja) | 1982-12-01 | 1982-12-01 | デ−タ解読装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57210778A JPS59101928A (ja) | 1982-12-01 | 1982-12-01 | デ−タ解読装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59101928A true JPS59101928A (ja) | 1984-06-12 |
| JPS6354251B2 JPS6354251B2 (enExample) | 1988-10-27 |
Family
ID=16594981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57210778A Granted JPS59101928A (ja) | 1982-12-01 | 1982-12-01 | デ−タ解読装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59101928A (enExample) |
-
1982
- 1982-12-01 JP JP57210778A patent/JPS59101928A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6354251B2 (enExample) | 1988-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4429300A (en) | High speed shift register circuit | |
| GB2175776A (en) | Dual edge clock address mark detector | |
| JPH0775343B2 (ja) | 同期検出回路及び方法 | |
| JPH0624356B2 (ja) | データ転送方式 | |
| US6898722B2 (en) | Parallel data transfer method and system of DDR divided data with associated transfer clock signal over three signal lines | |
| JPS59101928A (ja) | デ−タ解読装置 | |
| US6418176B1 (en) | Forwarded clock recovery with variable latency | |
| US4747106A (en) | Parity checker circuit | |
| JPS6354252B2 (enExample) | ||
| JPS648384B2 (enExample) | ||
| JPH0339424B2 (enExample) | ||
| JPS61201534A (ja) | 衝突検出機能付き送受信装置 | |
| JPS619057A (ja) | ゼロ插入回路 | |
| JPS60216653A (ja) | 半導体集積回路 | |
| JPH0149067B2 (enExample) | ||
| JP2632901B2 (ja) | 通信インタフェース方式 | |
| RU1789993C (ru) | Устройство дл редактировани элементов таблиц | |
| JP3088144B2 (ja) | Fifoリセット回路 | |
| JPS62284526A (ja) | デ−タ列変換回路 | |
| JPH0378819B2 (enExample) | ||
| JPS59188753A (ja) | パリテイ生成方法 | |
| KR100263048B1 (ko) | 듀얼 비트 엔알제트 데이타 전송방식 디스크 구동 기록장치의 어드레스 마크 검출장치 | |
| JPS648495B2 (enExample) | ||
| JPH0470040A (ja) | インターフェースバス拡張装置 | |
| JPH0390930A (ja) | デジタル式コンパレータ |