JPS6354251B2 - - Google Patents
Info
- Publication number
- JPS6354251B2 JPS6354251B2 JP57210778A JP21077882A JPS6354251B2 JP S6354251 B2 JPS6354251 B2 JP S6354251B2 JP 57210778 A JP57210778 A JP 57210778A JP 21077882 A JP21077882 A JP 21077882A JP S6354251 B2 JPS6354251 B2 JP S6354251B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- binary data
- serial
- output
- index
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 13
- 230000000630 rising effect Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57210778A JPS59101928A (ja) | 1982-12-01 | 1982-12-01 | デ−タ解読装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57210778A JPS59101928A (ja) | 1982-12-01 | 1982-12-01 | デ−タ解読装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59101928A JPS59101928A (ja) | 1984-06-12 |
| JPS6354251B2 true JPS6354251B2 (enExample) | 1988-10-27 |
Family
ID=16594981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57210778A Granted JPS59101928A (ja) | 1982-12-01 | 1982-12-01 | デ−タ解読装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59101928A (enExample) |
-
1982
- 1982-12-01 JP JP57210778A patent/JPS59101928A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59101928A (ja) | 1984-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0275585A1 (en) | Method of transmitting n-bit information words, information transmission system for carrying out the method, and encoding device and decoding device for use in the information-transmission system | |
| GB2175776A (en) | Dual edge clock address mark detector | |
| JPH0118615B2 (enExample) | ||
| JP5483170B2 (ja) | デジタル信号伝送装置及びデジタル信号伝送方法 | |
| JPH0775343B2 (ja) | 同期検出回路及び方法 | |
| EP0181517A1 (en) | Demodulator for an asynchronous binary signal | |
| US4481648A (en) | Method and system for producing a synchronous signal from _cyclic-redundancy-coded digital data blocks | |
| JPS6354251B2 (enExample) | ||
| JPS6354252B2 (enExample) | ||
| KR900000703B1 (ko) | 패리티(parity) 검출회로 | |
| EP0282924B1 (en) | Bipolar with eight-zeros substitution and bipolar with six-zeros substitution coding circuit | |
| JPH0338786B2 (enExample) | ||
| JPH0339424B2 (enExample) | ||
| JPH04329721A (ja) | データ受信方法 | |
| JP2632901B2 (ja) | 通信インタフェース方式 | |
| SU826562A1 (ru) | Многоканальный преобразователь кода во временной. интервал | |
| JP2848331B2 (ja) | ハザードフリー有限状態機械合成方式 | |
| JPS58182352A (ja) | デジタルデ−タ受信回路 | |
| JPS619057A (ja) | ゼロ插入回路 | |
| KR100314675B1 (ko) | 디지털 텔레비전의 양위상 디코더 | |
| JP3088144B2 (ja) | Fifoリセット回路 | |
| JPS5942505B2 (ja) | デ−タ信号検出回路 | |
| SU1169173A1 (ru) | Устройство дл преобразовани последовательного кода в параллельный | |
| SU605208A1 (ru) | Устройство дл сопр жени цифровой вычислительной машины с внешними устройствами | |
| SU1181155A1 (ru) | Преобразователь последовательного кода в параллельный |