JPS589974B2 - デイジタル加算器 - Google Patents

デイジタル加算器

Info

Publication number
JPS589974B2
JPS589974B2 JP51030923A JP3092376A JPS589974B2 JP S589974 B2 JPS589974 B2 JP S589974B2 JP 51030923 A JP51030923 A JP 51030923A JP 3092376 A JP3092376 A JP 3092376A JP S589974 B2 JPS589974 B2 JP S589974B2
Authority
JP
Japan
Prior art keywords
carry
adder
byte
boundary
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51030923A
Other languages
English (en)
Japanese (ja)
Other versions
JPS51134539A (en
Inventor
エベレツト・エム・シムプ
デビツト・エヌ・グツデイング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS51134539A publication Critical patent/JPS51134539A/ja
Publication of JPS589974B2 publication Critical patent/JPS589974B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
JP51030923A 1975-05-01 1976-03-23 デイジタル加算器 Expired JPS589974B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/573,656 US3987291A (en) 1975-05-01 1975-05-01 Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and location

Publications (2)

Publication Number Publication Date
JPS51134539A JPS51134539A (en) 1976-11-22
JPS589974B2 true JPS589974B2 (ja) 1983-02-23

Family

ID=24292864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51030923A Expired JPS589974B2 (ja) 1975-05-01 1976-03-23 デイジタル加算器

Country Status (5)

Country Link
US (1) US3987291A (enExample)
JP (1) JPS589974B2 (enExample)
DE (1) DE2616717C2 (enExample)
FR (1) FR2309925A1 (enExample)
GB (1) GB1522045A (enExample)

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JPS5378742A (en) * 1976-12-23 1978-07-12 Toshiba Corp Multiplication control system
JPS53123634A (en) * 1977-04-05 1978-10-28 Fujitsu Ltd Carry look ahead circuit
JPS5833572B2 (ja) * 1977-10-21 1983-07-20 株式会社東芝 情報処理方式
US4161784A (en) * 1978-01-05 1979-07-17 Honeywell Information Systems, Inc. Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
US4418383A (en) * 1980-06-30 1983-11-29 International Business Machines Corporation Data flow component for processor and microprocessor systems
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
JPS5953940A (ja) * 1982-09-21 1984-03-28 Nec Corp 倍精度演算回路
US4638449A (en) * 1983-06-15 1987-01-20 International Business Machines Corporation Multiplier architecture
US4677584A (en) * 1983-11-30 1987-06-30 Texas Instruments Incorporated Data processing system with an arithmetic logic unit having improved carry look ahead
US4700325A (en) * 1984-02-08 1987-10-13 Hewlett-Packard Company Binary tree calculations on monolithic integrated circuits
US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers
JPS61224037A (ja) * 1985-03-29 1986-10-04 Fujitsu Ltd 多ビツト入力演算素子を用いた演算方式
US4623982A (en) 1985-06-10 1986-11-18 Hewlett-Packard Company Conditional carry techniques for digital processors
US4764887A (en) * 1985-08-02 1988-08-16 Advanced Micro Devices, Inc. Carry-bypass arithmetic logic unit
US4737926A (en) * 1986-01-21 1988-04-12 Intel Corporation Optimally partitioned regenerative carry lookahead adder
EP0252511B1 (de) * 1986-07-11 1991-05-29 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren und Anordnung zur Verknüpfung von Operanden variabler Länge in Datenverarbeitungsanlagen
US4914617A (en) * 1987-06-26 1990-04-03 International Business Machines Corporation High performance parallel binary byte adder
EP0310456A3 (en) * 1987-10-01 1990-12-05 Sony Magnescale, Inc. Improvements in audio mixing
AU626847B2 (en) * 1987-11-16 1992-08-13 Intel Corporation Dual mode adder circuitry
US5047975A (en) * 1987-11-16 1991-09-10 Intel Corporation Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode
GB8904392D0 (en) * 1989-02-27 1989-04-12 Ibm An arithmetic logic unit for a graphics processor
US5097436A (en) * 1990-01-09 1992-03-17 Digital Equipment Corporation High performance adder using carry predictions
JPH05233219A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd 半導体集積回路のキャリー先取り回路
US5375078A (en) * 1992-12-15 1994-12-20 International Business Machines Corporation Arithmetic unit for performing XY+B operation
US5390135A (en) * 1993-11-29 1995-02-14 Hewlett-Packard Parallel shift and add circuit and method
US5883824A (en) * 1993-11-29 1999-03-16 Hewlett-Packard Company Parallel adding and averaging circuit and method
US5619441A (en) * 1994-10-14 1997-04-08 International Business Machines Corporation High speed dynamic binary incrementer
US6643765B1 (en) 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
GB2317466B (en) * 1996-09-23 2000-11-08 Advanced Risc Mach Ltd Data processing condition code flags
GB2317464A (en) * 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Register addressing in a data processing apparatus
GB2317467B (en) * 1996-09-23 2000-11-01 Advanced Risc Mach Ltd Input operand control in data processing systems
GB2317469B (en) * 1996-09-23 2001-02-21 Advanced Risc Mach Ltd Data processing system register control
GB2317465B (en) * 1996-09-23 2000-11-15 Advanced Risc Mach Ltd Data processing apparatus registers.
US5784602A (en) * 1996-10-08 1998-07-21 Advanced Risc Machines Limited Method and apparatus for digital signal processing for integrated circuit architecture
US6003125A (en) * 1997-01-24 1999-12-14 Texas Instruments Incorporated High performance adder for multiple parallel add operations
KR100475012B1 (ko) * 1997-10-08 2005-04-14 삼성전자주식회사 그룹데이터에대한산술연산을수행하는64비트산술연산기
US6272514B1 (en) * 1997-11-18 2001-08-07 Intrinsity, Inc. Method and apparatus for interruption of carry propagation on partition boundaries
US6301600B1 (en) * 1997-11-18 2001-10-09 Intrinsity, Inc. Method and apparatus for dynamic partitionable saturating adder/subtractor
US6269387B1 (en) * 1997-12-11 2001-07-31 Intrinsity, Inc. Method and apparatus for 3-stage 32-bit adder/subtractor
US6134576A (en) * 1998-04-30 2000-10-17 Mentor Graphics Corporation Parallel adder with independent odd and even sum bit generation cells
DE19857255C1 (de) * 1998-12-11 2000-08-03 Hartmut B Brinkhus Selbstkonfigurierendes modulares Elektroniksystem, insbesondere Computersystem
DE10008774A1 (de) * 2000-02-24 2001-08-30 Patrick Freiberger Längenflexible Grundstruktur der Datenverarbeitung
US6539413B1 (en) * 2000-03-15 2003-03-25 Agere Systems Inc. Prefix tree adder with efficient sum generation
WO2002046910A1 (en) * 2000-12-04 2002-06-13 University College Cardiff Consultants Limited Carry lookahead adder for different data types
DE10215784A1 (de) * 2002-04-10 2003-10-30 Infineon Technologies Ag Rechenwerk und Verfahren zum Subtrahieren
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8416251B2 (en) * 2004-11-15 2013-04-09 Nvidia Corporation Stream processing in a video processor
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US8683126B2 (en) * 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US9064333B2 (en) * 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8780123B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8681861B2 (en) * 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) * 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8489851B2 (en) * 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
MY177563A (en) * 2010-04-15 2020-09-20 Univ Malaya Parallel self-timed adder (pasta)
JP2015143949A (ja) * 2014-01-31 2015-08-06 富士通株式会社 演算プログラム、演算装置および演算方法
RU2635247C1 (ru) * 2016-12-21 2017-11-09 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Параллельный сумматор

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3188453A (en) * 1961-12-14 1965-06-08 Bell Telephone Labor Inc Modular carry generating circuits
US3571803A (en) * 1968-06-04 1971-03-23 Bell Telephone Labor Inc Arithmetic unit for data processing systems
GB1245441A (en) * 1968-08-27 1971-09-08 Int Computers Ltd Improvements in or relating to adders operating on variable fields within words
US3751650A (en) * 1971-06-28 1973-08-07 Burroughs Corp Variable length arithmetic unit
JPS5219745B2 (enExample) * 1971-12-23 1977-05-30

Also Published As

Publication number Publication date
DE2616717C2 (de) 1983-11-24
US3987291A (en) 1976-10-19
JPS51134539A (en) 1976-11-22
FR2309925A1 (fr) 1976-11-26
DE2616717A1 (de) 1976-11-11
FR2309925B1 (enExample) 1979-09-21
GB1522045A (en) 1978-08-23

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