JPS53123634A - Carry look ahead circuit - Google Patents

Carry look ahead circuit

Info

Publication number
JPS53123634A
JPS53123634A JP3871877A JP3871877A JPS53123634A JP S53123634 A JPS53123634 A JP S53123634A JP 3871877 A JP3871877 A JP 3871877A JP 3871877 A JP3871877 A JP 3871877A JP S53123634 A JPS53123634 A JP S53123634A
Authority
JP
Japan
Prior art keywords
look ahead
carry look
ahead circuit
circuit
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3871877A
Other languages
Japanese (ja)
Other versions
JPS566025B2 (en
Inventor
Takamitsu Tsuchimoto
Yasushi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3871877A priority Critical patent/JPS53123634A/en
Publication of JPS53123634A publication Critical patent/JPS53123634A/en
Publication of JPS566025B2 publication Critical patent/JPS566025B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To realize a very high-speed carry look ahead circuit which can be mounted in a high-density integration, by constituting the circuit by a high-speed switch element(specially, transmission gate TG).
JP3871877A 1977-04-05 1977-04-05 Carry look ahead circuit Granted JPS53123634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3871877A JPS53123634A (en) 1977-04-05 1977-04-05 Carry look ahead circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3871877A JPS53123634A (en) 1977-04-05 1977-04-05 Carry look ahead circuit

Publications (2)

Publication Number Publication Date
JPS53123634A true JPS53123634A (en) 1978-10-28
JPS566025B2 JPS566025B2 (en) 1981-02-09

Family

ID=12533095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3871877A Granted JPS53123634A (en) 1977-04-05 1977-04-05 Carry look ahead circuit

Country Status (1)

Country Link
JP (1) JPS53123634A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827444A (en) * 1985-08-05 1989-05-02 Mitsubishi Denki Kabushiki Kaisha Carry skip-ahead circuit for Manchester-type adder chain

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503549A (en) * 1973-05-14 1975-01-14
JPS5047532A (en) * 1973-08-27 1975-04-28
JPS51134539A (en) * 1975-05-01 1976-11-22 Ibm Digital adder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503549A (en) * 1973-05-14 1975-01-14
JPS5047532A (en) * 1973-08-27 1975-04-28
JPS51134539A (en) * 1975-05-01 1976-11-22 Ibm Digital adder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827444A (en) * 1985-08-05 1989-05-02 Mitsubishi Denki Kabushiki Kaisha Carry skip-ahead circuit for Manchester-type adder chain

Also Published As

Publication number Publication date
JPS566025B2 (en) 1981-02-09

Similar Documents

Publication Publication Date Title
JPS53123634A (en) Carry look ahead circuit
JPS53104068A (en) Planetary change gear
JPS5223251A (en) Semiconductor circuit
JPS5277569A (en) Logical circuit
JPS544047A (en) Switching circuit
JPS53101260A (en) Selective gate circuit
JPS5227663A (en) Multi-function electronic timepiece
JPS53132969A (en) Selective gate circuit
JPS53139963A (en) Flip flop circuit
JPS53110359A (en) Two-way photo coupler gate circuit
JPS5368047A (en) Input signal buffer circuit
JPS51142244A (en) Signal transmission circuit
JPS5324213A (en) Shift control circuit
JPS5399638A (en) Range hood
JPS5373952A (en) Flip-flop integrated circuit
JPS5379309A (en) Unit suitable for multi-branching data transmission line
JPS5275248A (en) Diode switch
JPS53111248A (en) Address selector circuit
JPS51146840A (en) Photogyrator circuit
JPS51123053A (en) Logic circuit
JPS529356A (en) Flipflop circuit
JPS5394807A (en) Combined switch network
JPS5423454A (en) Aplifier and oscillator using that oscillator
JPS51149764A (en) Lagical circuit
JPS52146540A (en) Three-level memory circuit