JPS5895849A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5895849A
JPS5895849A JP56193088A JP19308881A JPS5895849A JP S5895849 A JPS5895849 A JP S5895849A JP 56193088 A JP56193088 A JP 56193088A JP 19308881 A JP19308881 A JP 19308881A JP S5895849 A JPS5895849 A JP S5895849A
Authority
JP
Japan
Prior art keywords
chip
junction
lead frame
semiconductor device
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56193088A
Other languages
English (en)
Inventor
Toshinori Tanaka
田中　俊範
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56193088A priority Critical patent/JPS5895849A/ja
Publication of JPS5895849A publication Critical patent/JPS5895849A/ja
Pending legal-status Critical Current

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明け≠導体装置に係り、特に樹脂封止型の半導体装
置の構成材料に関するものである。
従来から樹脂封止型の半導体装置シリコン（８ｉ）チッ
プがリードフレームの金（Ａｕ）メッキ又は銀（Ａｇ）
メッキさｎ次面に４当なろう材？１更用してダイポンデ
ィングさｎている。該ｂｉ　チップのＡＪ砿極とＡｕ又
はＡｇメッキさｎた外部端子へは２０〜５０μｍφのＡ
ｕ＠によって３００〜４００°Ｃの温間でテールレス熱
圧着ポールボンディングさｎている。つ’！１）Ｓｉチ
ップ側ではＡｌ−Ａｕ接合が形成さｎ、外部端子はＡｕ
−Ａｕ又はＡｇ−Ａｕが形成さγＩ２る。こ扛らのＡ７
−Ａｕ接合やＡｇ−Ａｕ４ｉ１合では純金属と比べ硬く
てもろい。そして磁気抵抗の大きい金属間化合物全形成
（２、従来ルーズコンタクトの原因とさｎて来た。
さらに従来の樹脂封止型の半導体装置の欠点は。
生唯自動化によりスピード向上’１ｉｔｔり生産コスト
を下げたにもかかわらすに１１を多量に瀘用している為
材料費はかな９＾いものとなっていることである。
本発明の目的は、このような従来の樹脂封止型の半導体
装置の欠点を除いた半導体装置を提供することにある。
本発明の特徴は、リードフレームを用、いた半導体装置
において、このリードフレームの少なくとも半導体チッ
プが載置される側の表面の樹脂封止さ扛る領域に部分的
に又Ｆｉ帯状にアルｆ　ニウム層が設けらｎ、半導体チ
ップ上の端子とリードフレームの外部端子とがアルミニ
ウム合金線によって一続さｎている半導体装置にある。
そして、　Ａｌが部分的又は帯状に０，５〜ｌＯμｍめ
厚さで付いているリードフレームに半導体チップが固定
されていて１．ｆｉ！径が２０〜５０μｍのＡ１合金線
によって外部端子と半導体チップとが接続さｎ１樹脂に
よって封止さｎていることが好ましい。
本発明によｎば、貴金禰特にＡｕを使用せずに済むので
、従来の製造コストを向上させることなく、かつ、−気
的特性の優ｎた樹脂封止型半導体装置を供給することが
できる。
以下１図１ｆｉを用いて本発明の一実施例を詳細に説明
する。
＠１図は樹脂封止前の半導体装置の断面図である。タ゛
イボンディング部ｌ中外部端子２は従来ＡｕメッキやＡ
ｇメッキであったが、こｎを湿式メッキ法によらず膜厚
のコントロールの安定な真空蒸着法によジＡＪ膜３を形
成することでダイボンディング及びワイヤーボンディン
グを可能にさせた。
ダイボンディングにはＡＩ箔を隻用せずにＡｇペースト
及び半田等のろう材４で８１　　チップ５を安定に固定
することは可能である。８ｉ　チップ５のＡｌ電極６と
外部端子のＡｌ膜３との接続にはＡＪ線を使用して８ｉ
　チップ側、外部瑞子側共にＡｌ−ＡＪの接合とした。
ｄＡｌ−ＡＩ接合はＡｌ−Ａｕ接合やＡｇ−Ａｕ接合、
に比べ金属間化合物を形成しないので腐食性や電気的時
性が改善さｎる。しかしリードフレームのＡＪ　嘆は樹
脂封止さｎる外側に出ると８ｎ又はｂｎ−ｔ’ｂのメッ
キが出来なくなるのでＡｌは樹脂封止さｎる内側にのみ
部分的に付ける必要がある。この技術は現在実砲してい
るリードフレームへの部分Ａ、又は部分Ａｇ　メッキの
製造技術をもってすｎば容易なことである。
以下、実施例により説明する。第２図は本夷怖例のリー
ドフレームの図であり、第３図は樹脂封市前の本実癩例
の半導体装置の図である。リードフレームは４２％Ｎ１
−Ｆ’ｅ合金基板８にｋｌ膜９を部分的に付けたもので
ある。該リードフレームの製造は基板８の片面の全域に
Ａｌを真空蒸着し。
必要なＡ１４９にワックスを塗布することでマスクして
水酸化ナトリウム溶液にて不必要なＡＩをエツチングし
て、その後にワックスを有機溶剤にて除去したものであ
る。この製造は、自動化ラインｉ’Ｔ能であり１位置の
コントロール川に丸穴ｌＯを設−て連続つに処理したも
のである。該Ａ／蒸′ｙＩＩ幌厚はワイヤーボンティン
グ可能なように４μに設定して製造した。次にダイボン
ディング４１１に８１チツプ１２ｔダイボンデイングし
た。該ダイボンディングはＡｇベートを介してダイボン
ディングを行った。次に８１チツプ１２のＡｌ電極１３
とＡＪが蒸着さｎている外部端子１４を結合させるため
に３０μφのｋｌ−１％８１線１５をワイヤボンディン
グした。該ボンディングはＡｕ線ボンディングと同様な
超音波併用型の熱圧着ポールボンティング装置で実施し
た。該ボンディングはＡ／喧他極１３側はＡＩ、＠の先
端にＡＪ球を形成して熱圧着する方法で、ＡＪ球の形成
時にはＡｔ雰囲気を部分的に形成して電気放電を利用し
たトーチでＡＪ球を形成した。該ボンディング温度は２
００°Ｃ〜３θＯ０Ｃのヒータブロック上で行ったもの
でｋｌ−ｋｌの自己拡散を早め安定にボンディングが可
能であった。該ボンディング以降は従来と同様で樹脂封
止全行い、外装メッキを行った後。
半導体装置を個々に分線して製造完了した。
以上の材料構成で製造すｎば従来の工程を大きく変更す
ることなぐ、材料費を低減し、かつ特性的にも安定な半
導体装置を得らｎる。
なお１本実施例で４２％Ｎｉ−１”ｅ合金基板のリード
フレームを用いたが、さらに材料費を低減する目的でＣ
ｕ合金又ｎＦｅ主体の合金でも同様の効果が得らｎるこ
とは明らかである。また、リードフレームは第２図の形
状から第４図の形状に変更す扛ば部分的にＡｌ　ｔ−蒸
着する代りにＡＩ　をストライプ状に連続的に付けるこ
とが可能となりＡｌを基板に圧接する方法でも製造可能
であり、より合理的な製造方法も可能となる。またダイ
ボンティングにＡｇペーストを使用したが、他に３００
０Ｃ近辺に融点をもつろう材（例えばに’１３１３−８
ｎ−Ａでめｎば利用できるものであり、Ａｕ箔によるＡ
ｕ−８４接合も充分に可能である。
【図面の簡単な説明】
第１図は本発明の構成材料を説明する上で用いた樹１１
＆：ｔ１止前半導体装置の断面図、第２図は本発明の実
施例に用いたリードフレームの平面図、第３図は本発明
の実施例に用いた樹脂封止前の半導体装酸の８ｉ　チッ
プ部の平面図、第４図は第２図で示したリードフレーム
と形状が異なったリードフレームの平面図、である。 なお図において％　１ｅｌｌ＊１７・・・・・・ダイボ
ンディング部、２・・・・・・外部端子、３・・・・・
・Ａｌ膜、４・・・・・・ろう材、５＊１２・・・・・
・８ｉ　チップ、６＋１３・・・・・・Ａｒ４極、７・
・・・・・ＡＪ線、８・・・・・・４２チヘｉ−１”ｅ
基板　、９・・・・・・Ａ／　蒸着膜、１０・・・・・
・ガイド穴。 １４・・・・・・Ａｌ蒸着さｎた外部端子、１５・・・
・・・Ａｌ劣ｆ図

Claims (1)

  1. 【特許請求の範囲】 リードフレームを用いた半導体装置においで。 該リード・フレームの少なくとも半導体チップが載置さ
    ｎる側の表面の樹脂封止さｎる領域に部分的に又は帯状
    にアルミニウム層が設けらｎ、前記半導体チップ上の端
    子と前記リードフレームの外部４子とがアルミニウム合
    金線によって接続さｎていることを特徴とする半導体装
    置。
JP56193088A 1981-12-01 1981-12-01 半導体装置 Pending JPS5895849A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56193088A JPS5895849A (ja) 1981-12-01 1981-12-01 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56193088A JPS5895849A (ja) 1981-12-01 1981-12-01 半導体装置

Publications (1)

Publication Number Publication Date
JPS5895849A true JPS5895849A (ja) 1983-06-07

Family

ID=16302025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56193088A Pending JPS5895849A (ja) 1981-12-01 1981-12-01 半導体装置

Country Status (1)

Country Link
JP (1) JPS5895849A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0142447A2 (en) * 1983-11-14 1985-05-22 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Semiconductor package
US5888847A (en) * 1995-12-08 1999-03-30 Lsi Logic Corporation Technique for mounting a semiconductor die
CN103035535A (zh) * 2012-12-26 2013-04-10 常州银河世纪微电子有限公司 大电流/高压二极管的制备方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0142447A2 (en) * 1983-11-14 1985-05-22 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Semiconductor package
EP0142447A3 (en) * 1983-11-14 1987-05-13 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Semiconductor package
US5888847A (en) * 1995-12-08 1999-03-30 Lsi Logic Corporation Technique for mounting a semiconductor die
CN103035535A (zh) * 2012-12-26 2013-04-10 常州银河世纪微电子有限公司 大电流/高压二极管的制备方法

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