JPS588968U - 半導体素子用リ−ドフレ−ム - Google Patents

半導体素子用リ−ドフレ−ム

Info

Publication number
JPS588968U
JPS588968U JP10363581U JP10363581U JPS588968U JP S588968 U JPS588968 U JP S588968U JP 10363581 U JP10363581 U JP 10363581U JP 10363581 U JP10363581 U JP 10363581U JP S588968 U JPS588968 U JP S588968U
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor devices
pedestal
lead
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10363581U
Other languages
English (en)
Inventor
箕輪　文雄
五十嵐　巳喩輝
Original Assignee
日本インタ−ナシヨナル整流器株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本インタ−ナシヨナル整流器株式会社 filed Critical 日本インタ−ナシヨナル整流器株式会社
Priority to JP10363581U priority Critical patent/JPS588968U/ja
Publication of JPS588968U publication Critical patent/JPS588968U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図及び第２図は、従来の半導体素子用リードフレー
ムを有し、第１図は、平置き型リードフレームの平面図
、第２図は、縦型リードフレームの平面図、第３図及び
第４図は、本考案のリードフレームを示し、第３図は、
その一部切欠斜視図、第４図は、他の実施例を示す斜視
図である。 １１・・・リードフレーム、１２，１４．１５・・・短
冊片、１２ａ、１４ａ、１５ａ・・・台座部、１３・・
・半導体ペレット、１６・・・金属細線、１７・・・樹
脂モールド。

Claims (1)

    【実用新案登録請求の範囲】
  1. 複数の短冊片を有するように櫛歯状に形成したリードフ
    レームの先端を折り曲げて台座部を形成し、この台座部
    に半導体ペレットを塔載し得るようにしたことを特徴と
    する半導体素子用リードフレーム。
JP10363581U 1981-07-13 1981-07-13 半導体素子用リ−ドフレ−ム Pending JPS588968U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10363581U JPS588968U (ja) 1981-07-13 1981-07-13 半導体素子用リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10363581U JPS588968U (ja) 1981-07-13 1981-07-13 半導体素子用リ−ドフレ−ム

Publications (1)

Publication Number Publication Date
JPS588968U true JPS588968U (ja) 1983-01-20

Family

ID=29898242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10363581U Pending JPS588968U (ja) 1981-07-13 1981-07-13 半導体素子用リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS588968U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244895A (ja) * 1987-03-31 1988-10-12 Mitsubishi Electric Corp 半導体レ−ザの組立方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244895A (ja) * 1987-03-31 1988-10-12 Mitsubishi Electric Corp 半導体レ−ザの組立方法

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