JPS5882332A - 通信制御処理方式 - Google Patents

通信制御処理方式

Info

Publication number
JPS5882332A
JPS5882332A JP18065481A JP18065481A JPS5882332A JP S5882332 A JPS5882332 A JP S5882332A JP 18065481 A JP18065481 A JP 18065481A JP 18065481 A JP18065481 A JP 18065481A JP S5882332 A JPS5882332 A JP S5882332A
Authority
JP
Japan
Prior art keywords
input
write command
data
command
special write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18065481A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0126102B2 (enrdf_load_stackoverflow
Inventor
Masao Ikegami
池上　雅雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Usac Electronic Ind Co Ltd
Original Assignee
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usac Electronic Ind Co Ltd filed Critical Usac Electronic Ind Co Ltd
Priority to JP18065481A priority Critical patent/JPS5882332A/ja
Publication of JPS5882332A publication Critical patent/JPS5882332A/ja
Publication of JPH0126102B2 publication Critical patent/JPH0126102B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Bidirectional Digital Transmission (AREA)
JP18065481A 1981-11-11 1981-11-11 通信制御処理方式 Granted JPS5882332A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18065481A JPS5882332A (ja) 1981-11-11 1981-11-11 通信制御処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18065481A JPS5882332A (ja) 1981-11-11 1981-11-11 通信制御処理方式

Publications (2)

Publication Number Publication Date
JPS5882332A true JPS5882332A (ja) 1983-05-17
JPH0126102B2 JPH0126102B2 (enrdf_load_stackoverflow) 1989-05-22

Family

ID=16086976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18065481A Granted JPS5882332A (ja) 1981-11-11 1981-11-11 通信制御処理方式

Country Status (1)

Country Link
JP (1) JPS5882332A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0126102B2 (enrdf_load_stackoverflow) 1989-05-22

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