JPS5878454A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5878454A
JPS5878454A JP56160545A JP16054581A JPS5878454A JP S5878454 A JPS5878454 A JP S5878454A JP 56160545 A JP56160545 A JP 56160545A JP 16054581 A JP16054581 A JP 16054581A JP S5878454 A JPS5878454 A JP S5878454A
Authority
JP
Japan
Prior art keywords
film
electrode
silicon film
base body
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56160545A
Other languages
English (en)
Japanese (ja)
Other versions
JPH02863B2 (fr
Inventor
Yasuaki Hokari
穂苅 泰明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56160545A priority Critical patent/JPS5878454A/ja
Publication of JPS5878454A publication Critical patent/JPS5878454A/ja
Publication of JPH02863B2 publication Critical patent/JPH02863B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP56160545A 1981-10-08 1981-10-08 半導体装置の製造方法 Granted JPS5878454A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56160545A JPS5878454A (ja) 1981-10-08 1981-10-08 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56160545A JPS5878454A (ja) 1981-10-08 1981-10-08 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5878454A true JPS5878454A (ja) 1983-05-12
JPH02863B2 JPH02863B2 (fr) 1990-01-09

Family

ID=15717296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56160545A Granted JPS5878454A (ja) 1981-10-08 1981-10-08 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5878454A (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054425A (ja) * 1983-09-05 1985-03-28 Agency Of Ind Science & Technol 半導体装置の製造方法
JPH0555211A (ja) * 1991-08-27 1993-03-05 Hamamatsu Photonics Kk 配線形成方法
US5629236A (en) * 1994-07-26 1997-05-13 Kabushiki Kaisha Toshiba Method of manufacture of semiconductor device
US5759878A (en) * 1990-10-16 1998-06-02 Agency Of Industrial Science And Technology Method of fabricating semiconductor device having epitaxially grown semiconductor single crystal film

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054425A (ja) * 1983-09-05 1985-03-28 Agency Of Ind Science & Technol 半導体装置の製造方法
JPH0449775B2 (fr) * 1983-09-05 1992-08-12 Kogyo Gijutsuin
US5759878A (en) * 1990-10-16 1998-06-02 Agency Of Industrial Science And Technology Method of fabricating semiconductor device having epitaxially grown semiconductor single crystal film
US5926699A (en) * 1990-10-16 1999-07-20 Agency Of Industrial Science And Technology Method of fabricating semiconductor device having stacked layer substrate
JPH0555211A (ja) * 1991-08-27 1993-03-05 Hamamatsu Photonics Kk 配線形成方法
US5629236A (en) * 1994-07-26 1997-05-13 Kabushiki Kaisha Toshiba Method of manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH02863B2 (fr) 1990-01-09

Similar Documents

Publication Publication Date Title
EP0036137B1 (fr) Procédé de fabrication de dispositifs à semi-conducteurs
JPS61502922A (ja) 絶縁体上の半導体(soi)デバイス及びsoi ic製作法
EP0113522B1 (fr) Fabrication de dispositifs semi-conducteurs
US4414242A (en) Process for fabricating a semiconductor device
JPH05160153A (ja) 半導体装置の作製方法
JPS5878454A (ja) 半導体装置の製造方法
JPH0450746B2 (fr)
JPH05182983A (ja) 薄膜トランジスタの製造方法
JPS60154549A (ja) 半導体装置の製造方法
JPS5878455A (ja) 半導体装置の製造方法
JPS58192381A (ja) Mos電界効果トランジスタの製造方法
US5011783A (en) Forming selective single crystal regions in insulated pockets formed on silicon by energy beams and devices formed in the pockets
JPH0467336B2 (fr)
JPS5860560A (ja) 半導体装置の冗長回路およびそのフユ−ズ部切断方法
JPH0440858B2 (fr)
KR100275206B1 (ko) 엑사이머 레이저 방사에 의한 폴리실리콘 싱글일렉트론소자의 제조방법
JPS5814525A (ja) 半導体装置の製造方法
JPS5918629A (ja) 半導体装置の製造方法
JPH0629321A (ja) 薄膜トランジスタおよびその製造方法
JPS58165317A (ja) 半導体単結晶膜の製造方法
JPS6017911A (ja) 半導体装置の製造方法
JPS6336512A (ja) 半導体単結晶薄膜の製造方法
JPS58169971A (ja) 半導体装置およびその製造方法
JPH07131029A (ja) 薄膜トランジスタの製造方法
JPS62250655A (ja) 半導体装置およびその製造方法