JPS5873141A - マルチチツプlsiパツケ−ジ - Google Patents
マルチチツプlsiパツケ−ジInfo
- Publication number
- JPS5873141A JPS5873141A JP56170782A JP17078281A JPS5873141A JP S5873141 A JPS5873141 A JP S5873141A JP 56170782 A JP56170782 A JP 56170782A JP 17078281 A JP17078281 A JP 17078281A JP S5873141 A JPS5873141 A JP S5873141A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat sink
- recess
- heat
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56170782A JPS5873141A (ja) | 1981-10-27 | 1981-10-27 | マルチチツプlsiパツケ−ジ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56170782A JPS5873141A (ja) | 1981-10-27 | 1981-10-27 | マルチチツプlsiパツケ−ジ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873141A true JPS5873141A (ja) | 1983-05-02 |
| JPS624859B2 JPS624859B2 (https=) | 1987-02-02 |
Family
ID=15911267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56170782A Granted JPS5873141A (ja) | 1981-10-27 | 1981-10-27 | マルチチツプlsiパツケ−ジ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873141A (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62116440U (https=) * | 1986-01-14 | 1987-07-24 |
-
1981
- 1981-10-27 JP JP56170782A patent/JPS5873141A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62116440U (https=) * | 1986-01-14 | 1987-07-24 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS624859B2 (https=) | 1987-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100269528B1 (ko) | 고성능 멀티 칩 모듈 패키지 | |
| US6326696B1 (en) | Electronic package with interconnected chips | |
| TW502406B (en) | Ultra-thin package having stacked die | |
| JP4493121B2 (ja) | 半導体素子および半導体チップのパッケージ方法 | |
| US6111313A (en) | Integrated circuit package having a stiffener dimensioned to receive heat transferred laterally from the integrated circuit | |
| US20020175401A1 (en) | Semiconductor package with stacked chips | |
| JPH0548000A (ja) | 半導体装置 | |
| JPH07221218A (ja) | 半導体装置 | |
| JP2005217405A (ja) | 熱放出形半導体パッケージ及びその製造方法 | |
| KR20200135503A (ko) | 모놀리식 마이크로파 통합 회로(mmic) 냉각 구조 | |
| US6294838B1 (en) | Multi-chip stacked package | |
| CN218957731U (zh) | 用于集成电路的封装 | |
| JPH06224334A (ja) | マルチチップモジュール | |
| JP2882116B2 (ja) | ヒートシンク付パッケージ | |
| CN1319138C (zh) | 封装的半导体器件的形成方法 | |
| US6034425A (en) | Flat multiple-chip module micro ball grid array packaging | |
| CN100550360C (zh) | 具有底部散热的设备和系统及其制造方法 | |
| JP2000156460A (ja) | 半導体装置 | |
| JPS5873141A (ja) | マルチチツプlsiパツケ−ジ | |
| JPH06204355A (ja) | 半導体装置用パッケージ及び半導体装置 | |
| JP2007281201A (ja) | 半導体装置 | |
| JPS61137349A (ja) | 半導体装置 | |
| JPH08162575A (ja) | 半導体装置およびその製造方法 | |
| US20020050378A1 (en) | Double-layered multiple chip module package | |
| JPH0878616A (ja) | マルチチップ・モジュール |