JPS5864531A - I/o address control system - Google Patents

I/o address control system

Info

Publication number
JPS5864531A
JPS5864531A JP16300281A JP16300281A JPS5864531A JP S5864531 A JPS5864531 A JP S5864531A JP 16300281 A JP16300281 A JP 16300281A JP 16300281 A JP16300281 A JP 16300281A JP S5864531 A JPS5864531 A JP S5864531A
Authority
JP
Japan
Prior art keywords
address
processor
selection signal
address conversion
ilo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16300281A
Other languages
Japanese (ja)
Inventor
Junichi Sakakibara
榊原　純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16300281A priority Critical patent/JPS5864531A/en
Publication of JPS5864531A publication Critical patent/JPS5864531A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need for the address conversion of a program and an I/O, by providing an address conversion table between a processor and the I/O, and eliminating a difference between the I/O address definition of the processor side and the characteristic address of the I/O. CONSTITUTION:Address conversion is performed through a processor 1 which controls an I/O and an address conversion table 2 which inputs an I/O selection signal from the processor 1. The address conversion output is used as a selection signal for an I/O3 and the table is used to allow characteristic I/O addresses assigned to the I/O3 to correspond to I/O addresses that the processor side 1 requires.

Description

【発明の詳細な説明】 本発明はプログラム制御形装置のＩ１０アドレス制御方
式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an I10 address control scheme for program controlled devices.

従来のプログラム制御によるＩ１０制御方式では、プロ
セッサからのＩ１０選択信号（アドレスバス）’Ｉ１０
側でデコードしやすい様にＩ１０アドレスヲ定義し、ア
ドレス変換テーブルを介さずにいた。例えば複数の機能
を持つＬＳＩではそのＩ１０アドレスはＬＳＩ内部で連
続したＩ１０アドレスをデコードする様に定義されてい
る。In the conventional program-controlled I10 control method, the I10 selection signal (address bus) 'I10
The I10 address was defined so that it could be easily decoded on the side, without going through an address conversion table. For example, in an LSI having multiple functions, the I10 address is defined such that consecutive I10 addresses are decoded within the LSI.

ところが最近の様に装置が大形化し、一つのプロセッサ
で多種類のＩ　／　Ｏ６制御する様にカリ、Ｉ１０アド
レスが複雑多岐に渡る様になって来ると、各々のＩｌｏ
がデコードしやすい様に定義することが難しくなってき
た。この為、例えば同−ＬＳＩ内の機能モジュールのア
ドレスバス数のかけ離れ九Ｉ／（Ｊアドレスに定義する
ということが、従来の方式では難しいという欠点があっ
た。又、既存のＩｌｏを別の装置で使用するとき、その
装置におけるＩ１０アドレスが異なっているとＩｌｏ側
のデコーダを改造して変更するという欠点があった。However, as devices have recently become larger and I/O6 addresses have become more complex and diverse, with a single processor controlling many types of I/O6, each
It has become difficult to define it in a way that is easy to decode. For this reason, for example, the conventional method has the disadvantage that it is difficult to define the address buses of functional modules within the same LSI as 9 I/(J addresses. When used in a device with a different I10 address, there is a drawback that the decoder on the Ilo side must be modified to change the address.

本発明は、プロセッサとＩ／（Ｊとの間にアドレス変換
テーブル全役けることによりプロセッサ側で定義してい
るＩｌｏのアドレスをテーブルを索引することによりＩ
１０固有のアドレスに対応づけるものである。これによ
りプロセッサとＩｌｏとの間のＩ１０選択アドレスの一
致をとるものである。The present invention utilizes an address conversion table between the processor and I/(J) to index the Ilo address defined on the processor side.
10 unique addresses. This ensures that the I10 selection address between the processor and Ilo matches.

プログラム制御堰装置のＩ１０制御において、Ｉｌｏを
制御するプロセッサとプロセッサからのＩ／（Ｊ選択信
号（アドレスバス）を入力とするアドレス変換テーブル
全弁してアドレス変換を行い、その出力１Ｉ１０の選択
信号とするものでらる。In the I10 control of the program controlled weir device, the processor that controls Ilo and the address conversion table that receives the I/(J selection signal (address bus) from the processor as input) perform address conversion, and the output 1I10 selection signal There is something to be said.

このテーブルを用いることによりＩ１０に割り当てられ
た固有のＩ１０アドレスをプロセッサ側で欲するＩ１０
アドレスに対応させることができる。By using this table, I10 that wants a unique I10 address assigned to I10 on the processor side.
It can be made to correspond to an address.

次に本発明の一実施例について第１図を用いて説明する
。図において、１はｌ１０ｉ制御するプロセッサでおり
、プロセッサからのＩ１０選択信号（アドレスバス）は
Ａである。２はこの選択信号を入力とするアドレス変換
テーブルでアシ、その出力はＮである。３はテーブルの
出力ｘ２選択信号とするＩｌｏである。Ｄはデータバス
である。Next, one embodiment of the present invention will be described using FIG. 1. In the figure, 1 is a processor that controls I10i, and A is the I10 selection signal (address bus) from the processor. 2 is an address conversion table which receives this selection signal as an input, and its output is N. 3 is Ilo which is used as the table output x2 selection signal. D is a data bus.

ここで、Ｉｌｏのアドレスが１０」と「１」という２つ
の機能金持つＬＳＩで、プロセッサの制御（すなわちプ
ログラム〕はそのＩｌｏのアドレスを例えば「７」と「
３」と云う様に定義しているとすると、このプログラム
全アドレス変換テーブルなしで直接プロセッサからＩ１
０’ｉ制御することはできない。ところが、アドレス変
換テーブルを用い第２図に示す様に対応づけておけば、
容易にアドレス変換ができそのままプログラムの変更も
Ｉｌｏの変更もなくて済む。Here, in an LSI with two functional funds whose Ilo addresses are ``10'' and ``1'', the processor control (i.e., program) sets the Ilo addresses to ``7'' and ``1'', for example.
3", this program can directly access I1 from the processor without any address conversion table.
0'i cannot be controlled. However, if you use the address translation table and make the correspondence as shown in Figure 2,
Address translation can be easily performed, and there is no need to change the program or change Ilo.

アドレス変換テーブルとしては）Ｉ、ＡＭ（ランダムア
クセスメモリー）やＲＯＭ（リードオンリーメモリー）
ヲ使用することができＲＡＭ′ｊｋ用いた時はダイナミ
ックにＩ／（Ｊアドレスを変更することができる為、多
種のプログラムを使用する装置のＩ１０アドレスのくい
違いを吸収することができる。As an address conversion table) I, AM (Random Access Memory) and ROM (Read Only Memory)
Since the I/(J address can be dynamically changed when RAM'jk is used, it is possible to absorb differences in the I10 address of devices using various programs.

本発明はプロセッサとＩｌｏとの間にアドレス変換テー
ブルを設けることによυプロセッサ側の■１０アドレス
の定義とＩ１０固有のアドレスのくい違いを吸収し、プ
ログラム及びＩｌｏのアドレス変更をなくするものであ
る。By providing an address conversion table between the processor and Ilo, the present invention absorbs the discrepancy between the definition of ■10 address on the υ processor side and the address specific to I10, and eliminates the need to change the address of the program and Ilo. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のブロック図、第２図はアド
レス変換テーブルの動作を説明するものである。 １・・・・・・プロセッサ、２・・・・・・アドレス変
換テーブル、３・・・・・・Ｉｌｏ、Ａ・・・・・・プ
ロセッサからのＩ１０選択信号（アドレスバス）、Ｎ・
・・・・・テーブルからのＩ１０選択信号、Ｄ・・・・
・・データバス。 ５− り 寮１　記 寮Ｚ図FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 explains the operation of an address translation table. 1... Processor, 2... Address conversion table, 3... Ilo, A... I10 selection signal (address bus) from processor, N.
...I10 selection signal from the table, D...
...Data bus. 5- Dormitory 1 Dormitory Z diagram

Claims (1)

【特許請求の範囲】[Claims] プログラム制御形装置のＩ　／　Ｏ！ｌＪ御においで、
Ｉ１０’ｉ制御するプロセッサと、プロセッサからのＩ
１０選択信号（アドレスバス）を入力とするアドレス変
換テーブルと、そのテーブルからの出力アドレスを選択
信号とするＩ／（Ｊとを具備し、プロセッサから見たＩ
１０選択アドレスをそのＩ１０固有の選択アドレスに束
縛されることたく自由に設定することができることを特
徴とする■１０アドレス制御方式。I/O of program controlled devices! Come to LJ,
I10'i controlling processor and I from the processor
10 selection signal (address bus) as input, and I/(J) that uses the output address from the table as a selection signal.
(1) A 10-address control system characterized in that the 10-selected address can be freely set without being constrained by the I10-specific selection address.
JP16300281A 1981-10-13 1981-10-13 I/o address control system Pending JPS5864531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16300281A JPS5864531A (en) 1981-10-13 1981-10-13 I/o address control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16300281A JPS5864531A (en) 1981-10-13 1981-10-13 I/o address control system

Publications (1)

Publication Number Publication Date
JPS5864531A true JPS5864531A (en) 1983-04-16

Family

ID=15765325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16300281A Pending JPS5864531A (en) 1981-10-13 1981-10-13 I/o address control system

Country Status (1)

Country Link
JP (1) JPS5864531A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176163A (en) * 1984-02-22 1985-09-10 Fanuc Ltd Address selection system of input/output board
JPS62247445A (en) * 1986-03-28 1987-10-28 Nec Corp Selection controller for storage device
JPH07191904A (en) * 1993-11-12 1995-07-28 Internatl Business Mach Corp <Ibm> Apparatus and method for conversion of i/o address into memory address

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120935A (en) * 1974-03-11 1975-09-22
JPS5295939A (en) * 1976-02-06 1977-08-12 Nec Corp Common contrl device for input/output

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120935A (en) * 1974-03-11 1975-09-22
JPS5295939A (en) * 1976-02-06 1977-08-12 Nec Corp Common contrl device for input/output

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176163A (en) * 1984-02-22 1985-09-10 Fanuc Ltd Address selection system of input/output board
JPS62247445A (en) * 1986-03-28 1987-10-28 Nec Corp Selection controller for storage device
JPH07191904A (en) * 1993-11-12 1995-07-28 Internatl Business Mach Corp <Ibm> Apparatus and method for conversion of i/o address into memory address

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