JPS61175748A - Address decoding system for microprocessor - Google Patents

Abstract

PURPOSE:To decrease the number of output bits of an address decoder by distributing a read-only device and a write-only device into the same address space of a microprocessor. CONSTITUTION:An address decoder 2 decodes a high-order address signal 7 of a microprocessor 1 and delivers four selection signals 12-15. The selection signals 13-15 are connected to the read/write devices 4 and 5 as well as to a write-only device 6. While the selection signal 12 is connected to both a read- only device 3 and a write-only device 16. Therefore the same address space is allocated to both devices 3 and 16. When the processor 1 reads the signals given from the device 3, both devices 3 and 16 are selected by the decoder 2. Then the signals sent from the device 3 are read by a read control signal 11. In the same way, the decoder 2 selects both devices 3 and 16 and writes signals to the device 16 by a write control signal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address decoding method in a microprocessor application circuit.

(Prior Art) Conventionally, an address decoder of a microprocessor decodes several high-order bits of an address signal of the microprocessor, and uses each signal as a selection signal for each device (ROM, RAM, I10 port, etc.). In other words, it was common for one device to correspond to one continuous address space. Figure 2 shows a conventional decoder circuit. In the figure, among the address outputs of the microprocessor 1.

The upper several bits are decoded by the address decoder 2 to generate selection signals 12-15, which select each device 3-6 for input/output.

(Problems to be Solved by the Invention) However, if the number of devices is large and all the devices cannot be allocated to the entire address space, the decoder circuit becomes complicated because it also decodes the lower bits of the address. Also, if the number of devices exceeds the number of output bits of the decoder IC, the decoder I
There is a drawback that the number of Cs has to be increased.

In the example shown in Figure 2, if the number of output bits of address decoder 2 is only 4, or if the address decoder has already decoded the entire address space of the microprocessor, selection signals No. 5 are additionally required. When this happens, it is necessary to add an address decoder 2.

The present invention aims to improve the above-mentioned drawbacks.

(Means for Solving the Problems) A feature of the present invention for achieving the above object is that it includes a microprocessor and a plurality of external devices that transmit and receive data to and from the microprocessor. In a microprocessor address decoding method in which an external device is selected by decoding an address signal, a read-only device that sends data to the microprocessor and a write-only device that receives data from the microprocessor are selected from among the external devices. The purpose is to allocate them to the same address space of microprocessors.

(Operation) The same address space is assigned to a read-only device such as a ROM and a write-only device such as an output port, and both are selected at the same time.

However, since the microprocessor does not read and write at the same time, two devices with the same address will not interfere, and the two devices will operate perfectly normally. Therefore, a large number of external devices can be connected to a small address space.

(Embodiment) FIG. 1 shows a decoder circuit according to the present invention. An address decoder 2 that decodes a high-order address signal 7 of a microprocessor 1 outputs four selection signals 12-Is, while five external devices The 0 selection signals 13.14.15 to which 3, 4.degree.

The selection signal 12 is connected to both the read-only device 3 and the write-only device 16, so that the devices 3 and 16 are assigned the same address space.

When the microprocessor 1 reads a signal from the device 3, the decoder 2 selects both devices 3 and 16, and then the read control signal 11 reads the signal from the device 3. Similarly, when writing a signal to device 16, after selecting both devices 3 and 16 by decoder 2, the signal is written to device 16 by write control signal 10.

Since the read control signal 11 and the write control signal 10 are never output at the same time, the two devices 3 and 16 do not interfere with each other even though they are assigned the same address.

(Effects of the Invention) As described above, the present invention can reduce the number of output bits of an address decoder by allocating a read-only device and a write-only device to the same address space. In particular, when the number of output bits of the decoder is slightly insufficient, or when decoding the entire address space of the microprocessor is only slightly insufficient, using this method reduces the number of decoder ICs and has a large effect on circuit implementation. .

[Brief explanation of drawings]

FIG. 1 shows a decoder circuit according to the present invention, and FIG. 2 shows a conventional decoder circuit. 1-m-microprocessor, 2-m-address decoder. 3.4.5,6,16--External devices. 7.8-m-address signal, 9-m-data signal, 1
0-11 write control signal. 11-11 read control signal, 12-15-m- selection signal.

Claims (1)

[Claims] In an address decoding method for a microprocessor, which has a microprocessor and a plurality of external devices that exchange data with the microprocessor, the external device is selected by decoding an address signal from the microprocessor. Among them, a read-only device that sends data to the microprocessor and a write-only device that receives data from the microprocessor.
A microprocessor address decoding method characterized by assigning to the same address space of the microprocessor.