JPH07109597B2 - Microcomputer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a RAM (random access memory) mapped I
/ O-type one-chip microcomputer.

Conventional technology RAM-mapped I / O type one-chip microcomputer
RAM for address allocation for accessing the I / O ports by branching the control signal line supplied from the instruction decoder provided in the CPU (Central Processing Unit) to the RAM and connecting to each I / O port Since the control signal is shared with the RAM, the I / O port register and the data register can be added by simply decoding the address signal. Further, since there is no control instruction dedicated to the I / O port and there is no control signal line for executing this, the scale of the instruction decoder that outputs the control signal can be reduced.

By the way, in such a conventional microcomputer, each I / O
The ports are addressed with different addresses. Conversely, only one I / O port can be addressed by one address.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the application of a microcomputer, it is often the case that two devices are simultaneously moved (interlocked) by the output of the microcomputer. For example, driving a motor and driving an LED (light emitting diode) for indicating the operating state of the motor.

There are also cases where you want to initialize multiple I / O ports at the same time. Further, there is a case where it is desired to equivalently change the positions of one I / O port and another I / O port, but it is difficult or impossible for the conventional microcomputer to deal with these.

An object of the present invention is to provide a microcomputer that solves such a problem.

Means for Solving the Problems To achieve the above object, the present invention comprises an instruction decoder provided in a CPU, a RAM to which a control signal from the instruction decoder is supplied, and a plurality of I / O ports. In a RAM-mapped I / O type one-chip microcomputer in which the address allocation for accessing the I / O port is arranged in the RAM address space, the address data from the address bus is decoded in each I / O port. A plurality of address decoders having different address values from each other, and an address different from the addresses of the plurality of address decoders and also different for each I / O port, and based on the switching data from the data bus, A switching RAM for switching a plurality of address decoders and an address decoder selected by the switching RAM. RA that takes in data from the data bus when the address data to be input is input to the I / O port
M and M are provided in the I / O port.

Operation For example, in the conventional example, one I / O port can be addressed only by one RAM address, but in the configuration of the present invention, one I / O port can be addressed by a plurality of RAM addresses. This is because the address value of the address decoder of the I / O port can be switched among multiple addresses. The switching is controlled by giving the switching RAM data to the switching means accessed at another address different from the RAM address decoded by the address decoder.

Thus, by switching the address value of the address decoder, the I / O port is set as if its position had moved or replaced with another I / O port.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. In the figure, (1) is a control bus controller provided in the CPU, the output of which is supplied to the RAM (3) through the control bus (2) and the first I / O.
It is also supplied to the port (4) and the second I / O port (5). On the other hand, the output of the address bus controller (6) formed outside the CPU is also RAM through the address bus (7).
(3) and the first and second I / O ports (4) and (5). (8) is a data bus, RAM (3) and first and second I / O ports (4) (5)
It is connected to the. Although only two I / O ports are shown for simplification of the drawing, a large number of I / O ports connected in the same manner are actually provided.

Each I / O port is provided with a RAM (RM ₁ ) (RM ₂ ), but in this embodiment, _two address decoders associated with this RAM (RM ₁ ) (RM ₂ ) are prepared. ing.
(A ₁ ) (B ₁ ) and (A ₂ ) (B ₂ ) denote their address decoders.

These address decoders are switched based on other addresses and RAM data. (C ₁ ) and (C ₂ ) are switching RAMs provided in the respective I / O ports (4) and (5) for performing the switching, and include an address signal from the address bus (7) and a data bus ( The address decoder is switched in response to the switching data from 8).

Now, the address decoder (A ₁ ) in the first I / O port (4) has an address value of N ₁ , while the address decoder (B ₁ )
Is set the address value in N _2, the address decoder (A ₂₎ in the second I / O port (5) is N _2, the address decoder (B ₂₎ is respectively address value N ₁ is set It is assumed that the switching signals (RAM data) input to the switching RAMs (C ₁ ) and (C ₂ ) are 2 bits, and the switching relationship is as follows.

Here, A ₁ , A ₂ , B ₁ and B ₂ described in the columns of the first I / O port (4) and the second I / O port (5) depend on the contents of the 2-bit RAM data. The selected address decoder is shown, and N ₁ or N ₂ shown in <> indicates the selected address value.

In such a case, since the first I / O port (4) is set to the address value N ₁ and the second I / O port (5) is set to the address value N ₂ in the above (a), the address bus controller When the RAM address given from (6) is N ₁ , the first I
Only the / O port (4) is addressed, and when it is N ₂ , only the second I / O port (5) is addressed.

In the (b), RAM address second I / O port N ₁ is the first I / O port in N ₂ is addressed. Similarly, in (c), the RAM address is N ₁ , both the first I / O port and the second I / O port are addressed, and neither is addressed at RAM address N ₂ . Finally, in (d), both I / O ports are addressed by RAM address N ₂ , and neither is addressed by N ₁ .

Therefore, from the above, when it is desired to initialize the first and second I / O ports (4) and (5) at the same time, the same initial data is set in the RAM (RM) by changing the state to (c) or (d). ₁ ) (RM
₂ ) to give. Further, the first and second I / O ports (4) and (5) can be made to perform the interlocking function other than initialization by the same instruction.

Next, the operation performed in the first I / O port (4) is
If you want to use the first I / O port (4) to perform the operation that was performed on the second I / O port (5) on the first I / O port (5), It may be performed in the state of (b). In this case, it is equivalent to exchanging the positions of the first I / O port and the second I / O port.

Although the present invention has been described above according to the embodiment, the present invention is not limited to this embodiment, and various changes and modifications can be made without departing from the scope of the invention described in the claims. It is possible. For example, three or more I / O ports or all I / O ports may be provided with the above configuration, or only one I / O port may be provided with the above configuration. Nor. In addition, the switching signals in the above (a) to (d) and the first and second I /
The relationship with the address values of the O ports (4) and (5) may be arbitrarily changed. Further, the number of address decoders prepared for each I / O port (hence the number of switching address values) is not limited to two as shown in the figure.

As described above, according to the present invention, one I / O port is connected to a plurality of Rs.
It can be addressed by AM address. Therefore, it is possible to initialize multiple I / O ports at the same time with a single instruction, or to link functional operations other than initialization. In addition, the use as a microcomputer, such as the position of the I / O port can be changed equivalently,
In addition, the functional value is increased.

Further, since the address decoder can be individually switched for each I / O port, the address combination of a plurality of I / O ports can be achieved by software, and it is not necessary to make the combination by hardware. Therefore, there is an effect that the applicability is good, the hardware connection is simple, and the size of the chip itself can be kept small.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. (1) …… Control bus controller, (2) …… Control bus, (3) …… RAM, (4) …… First I / O port, (5) …… Second I / O port, (7) …… Address bus, (8) …… Data bus,
(A ₁ ) (B ₁ ) (A ₂ ) (B ₂ ) …… Address decoder, (RM
₁ ) (RM ₂ ) …… RAM in I / O port, (C ₁ ) (C ₂ ) …… RAM for switching, (N ₁ ) (N ₂ ) …… Address value.

Claims (1)

[Claims] 1. An instruction decoder provided in a CPU, a RAM to which a control signal from the instruction decoder is supplied, and a plurality of I's.
RAM-mapped with / O port and address allocation for accessing the I / O port arranged in the RAM address space
In the I / O type one-touch microcomputer, in each of the I / O ports, a plurality of address decoders having different address values for decoding address data from the address bus, and an address different from the addresses of the plurality of address decoders are used. A switching RAM that has a different address for each I / O port and that switches the plurality of address decoders based on the switching data from the data bus, and decodes by the address decoder selected by the switching RAM. RA that takes in data from the data bus when the address data to be input is input to the I / O port
A microcomputer having M and.