JPS56118152A - Control system for retrial - Google Patents

Control system for retrial

Info

Publication number
JPS56118152A
JPS56118152A JP2256180A JP2256180A JPS56118152A JP S56118152 A JPS56118152 A JP S56118152A JP 2256180 A JP2256180 A JP 2256180A JP 2256180 A JP2256180 A JP 2256180A JP S56118152 A JPS56118152 A JP S56118152A
Authority
JP
Japan
Prior art keywords
memory
retrial
controller
control
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2256180A
Other languages
Japanese (ja)
Inventor
Shuji Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2256180A priority Critical patent/JPS56118152A/en
Publication of JPS56118152A publication Critical patent/JPS56118152A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE:To enable the control of retrial with less amount of hardware, by adding the function for retrial control with each device requested with data processing. CONSTITUTION:A central controller CPU, memory controller 2, and input and output controller 3 are connected to a data processor 1 via a common bus l. Memory devices 4, 4a are connected to a memory controller 2, and if the corresponding memory address can be used according to the memory access request from CPU or input and output controller 3, the memory access request is made to the memory devices 4, 4a and the data transfer is made. The memory devices 4, 4a are provided with a memory section 6 which stores and reads out or writes in the data or instruction and detects error with the confirmation of the result, and retrial control section RC which restarts the memory section 6. Thus, the retrial control can be made with the device receiving starting.
JP2256180A 1980-02-25 1980-02-25 Control system for retrial Pending JPS56118152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2256180A JPS56118152A (en) 1980-02-25 1980-02-25 Control system for retrial

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2256180A JPS56118152A (en) 1980-02-25 1980-02-25 Control system for retrial

Publications (1)

Publication Number Publication Date
JPS56118152A true JPS56118152A (en) 1981-09-17

Family

ID=12086270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2256180A Pending JPS56118152A (en) 1980-02-25 1980-02-25 Control system for retrial

Country Status (1)

Country Link
JP (1) JPS56118152A (en)

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