ES8104593A1 - Cycle steal mechanism - Google Patents

Cycle steal mechanism

Info

Publication number
ES8104593A1
ES8104593A1 ES493786A ES493786A ES8104593A1 ES 8104593 A1 ES8104593 A1 ES 8104593A1 ES 493786 A ES493786 A ES 493786A ES 493786 A ES493786 A ES 493786A ES 8104593 A1 ES8104593 A1 ES 8104593A1
Authority
ES
Spain
Prior art keywords
memory
data
towards
unit
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES493786A
Other languages
Spanish (es)
Other versions
ES493786A0 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES493786A0 publication Critical patent/ES493786A0/en
Publication of ES8104593A1 publication Critical patent/ES8104593A1/en
Expired legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Programmable Controllers (AREA)

Abstract

Input/output controller device for data transfer. The controlling device (2), which functions by monociclic interruption, transfers the data from a memory (7) of a central computer (1) towards a plurality of units (3, 4, 5, 6). The device (2) bases its performance in a micro-order (11), a control program memory (12) unit, a direct memory access controller unit (13) and a programmable interruption control unit (15); all of them are connected to a general line (16) of entry/exit. The system allows to transfer data from the memory (7) towards the memory (12) of the controller (2), while data are being transmitted from or towards such memory (7). (Machine-translation by Google Translate, not legally binding)
ES493786A 1979-07-30 1980-07-29 Cycle steal mechanism Expired ES8104593A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6226279A 1979-07-30 1979-07-30

Publications (2)

Publication Number Publication Date
ES493786A0 ES493786A0 (en) 1981-04-01
ES8104593A1 true ES8104593A1 (en) 1981-04-01

Family

ID=22041308

Family Applications (1)

Application Number Title Priority Date Filing Date
ES493786A Expired ES8104593A1 (en) 1979-07-30 1980-07-29 Cycle steal mechanism

Country Status (5)

Country Link
JP (1) JPS5820061B2 (en)
AU (1) AU534605B2 (en)
BR (1) BR8004730A (en)
CA (1) CA1149070A (en)
ES (1) ES8104593A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01116846U (en) * 1988-02-01 1989-08-07

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108732A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Direct memory access system
JPS581811B2 (en) * 1977-11-04 1983-01-13 富士通株式会社 Direct memory access control method
JPS54127235A (en) * 1978-03-27 1979-10-03 Toshiba Corp Direct memory access unit
JPS5549728A (en) * 1978-10-04 1980-04-10 Hitachi Ltd Data transfer system

Also Published As

Publication number Publication date
BR8004730A (en) 1981-02-10
ES493786A0 (en) 1981-04-01
JPS5621223A (en) 1981-02-27
AU534605B2 (en) 1984-02-09
CA1149070A (en) 1983-06-28
AU5908180A (en) 1981-02-05
JPS5820061B2 (en) 1983-04-21

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