JPS53108732A - Direct memory access system - Google Patents

Direct memory access system

Info

Publication number
JPS53108732A
JPS53108732A JP2351377A JP2351377A JPS53108732A JP S53108732 A JPS53108732 A JP S53108732A JP 2351377 A JP2351377 A JP 2351377A JP 2351377 A JP2351377 A JP 2351377A JP S53108732 A JPS53108732 A JP S53108732A
Authority
JP
Japan
Prior art keywords
memory access
access system
direct memory
microprocessor
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2351377A
Other languages
Japanese (ja)
Inventor
Shozo Satake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2351377A priority Critical patent/JPS53108732A/en
Publication of JPS53108732A publication Critical patent/JPS53108732A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To prevent the performance of a microprocessor from deteriorating, by executing the cycle steal making use of the time needed for the microprocessor so as to determine the operation following the identification of the instruction when the microprocessor inputs the instruction.
JP2351377A 1977-03-04 1977-03-04 Direct memory access system Pending JPS53108732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2351377A JPS53108732A (en) 1977-03-04 1977-03-04 Direct memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2351377A JPS53108732A (en) 1977-03-04 1977-03-04 Direct memory access system

Publications (1)

Publication Number Publication Date
JPS53108732A true JPS53108732A (en) 1978-09-21

Family

ID=12112521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2351377A Pending JPS53108732A (en) 1977-03-04 1977-03-04 Direct memory access system

Country Status (1)

Country Link
JP (1) JPS53108732A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621223A (en) * 1979-07-30 1981-02-27 Ibm Cycle steal mechanism
JPS61213957A (en) * 1985-03-20 1986-09-22 Fujitsu Ltd Bus arbitration system
JPH01290057A (en) * 1988-05-17 1989-11-21 Pfu Ltd Bus control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621223A (en) * 1979-07-30 1981-02-27 Ibm Cycle steal mechanism
JPS5820061B2 (en) * 1979-07-30 1983-04-21 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション cycle steel mechanism
JPS61213957A (en) * 1985-03-20 1986-09-22 Fujitsu Ltd Bus arbitration system
JPH01290057A (en) * 1988-05-17 1989-11-21 Pfu Ltd Bus control system

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