JPS61213957A - Bus arbitration system - Google Patents

Abstract

PURPOSE:To eliminate the limitation of the number of connectable device in a clock-synchronizing daisy chain type bus arbitration system by stopping a clock temporarily when a device distant from an arbiter takes the leadership in bus use. CONSTITUTION:Plural devices 31-33 are connected to a bus 2 extending from a processor board 1 which has a microprocessor 11 and an arbiter circuit 12 and a bus leadership giving signal BGR is sent from the arbiter circuit 12 to the devices 31-33 in order on a daisy chain basis. Normal clock operation is performed for devices close to the arbiter circuit 12, but the bus clock signal BCLK is stopped for a time long enough to send the BGR from the rising or falling of the signal BGR for devices distant from the arbiter circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus arbitration system in microcomputer systems and the like, and particularly to a daisy chain type bus arbitration system for clock synchronous buses.

[Conventional technology]

An arbiter circuit is provided in a microcomputer system in which a microprocessor and a plurality of devices are connected via a bus.

When information is exchanged between a microprocessor and a device or between devices via a bus, the device or microprocessor that wants to take control of the bus issues a request to that effect to the arbiter circuit, and the arbiter circuit satisfies the conditions. The device is given bus control.

Such bus arbitration methods include a clock asynchronous method and a clock synchronous method.

Although the clock asynchronous type is not directly related to the present invention, its basic operation is to exchange signals between devices and between devices and an arbiter circuit in an acknowledgment manner using unsynchronized clock signals. . Although this method has the advantage that it can be applied even if the distance between the arbiter circuit and the device is large, the time required for acknowledgment is large, and high-speed signal conversion is not possible, and the circuit becomes complicated.

' On the other hand, the clock signal transmission type synchronizes the signal transmission with the clock signal, and the arbitration time is short and the circuit is simple. The clock synchronization method includes a parallel method in which a bus initiative grant signal is applied to each device in parallel n, and a daisy chain method in which it is applied in a daisy chain manner.

The present invention relates to a daisy chain system.

[Problem that the invention seeks to solve]

In daisy-chain type clock-synchronized bus arbitration, there is a limit to the transmission time of signals related to arbitration due to synchronization with a fixed clock cycle, so devices near the arbiter circuit are given bus control in a short time. A signal may arrive, but the end device in which it is daisy-chained cannot be reached within one clock pulse. especially,
If the clock frequency is increased to increase the transmission speed, the problem arises that (1) the clock pulse period becomes shorter, which greatly limits the number of devices that can be connected to the bus.

This problem does not occur with the pulse method, but the pulse method requires complex circuitry and large equipment capacity.

Therefore, even in the case of a clock synchronous daisy chain type arbitration system, it is desired to improve the overall performance by increasing the frequency while not being limited by the number of connectable devices.

[Failure to solve the problem]

In view of the above-mentioned problems, the present invention provides that when a plurality of devices are connected to a bus and the plurality of devices mutually transmit information via the bus in synchronization with clock signals, the device that has issued the bus control request is In a bus arbitration method in which bus dominance is granted to a plurality of devices connected in a daisy chain to acquire bus dominance, a predetermined number of pulses of the clock signal are applied when a desired device acquires bus dominance. To provide a bus arbitration method which is characterized in that it is prohibited.

[For production]

Those located near the arbiter circuit and capable of acquiring bus ownership in a short time perform bus ownership acquisition operations using the normal clock. On the other hand, if the arbiter circuit is far from the arbiter circuit and requires time to acquire bus control, the clock pulses are stopped (thinned) by the time required.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of an arbitration system as an embodiment based on the present invention. In FIG. 1, the system is composed of a processor board 1 having a microprocessor (μP) 11 and an arbiter circuit 12, a bus 2, and a device section 3 consisting of a plurality of devices 31 to 33 connected via the bus. There is. Devices 31-3
3 is, for example, a memory unit, peripheral equipment, etc.
□In Figure 1, the bus initiative grant signal BGR
sequentially from the arbiter circuit 12 to the devices 31, 32.3
3 and is propagated in a daisy chain. Therefore, the first and second devices 31 in the vicinity of the arbiter circuit 12
, 32 in a short time, but it takes a considerable amount of time to reach the final stage device 33.

In FIG. 1, BGRi indicates a bus initiative grant signal to the device entrance, and BGRo indicates a bus initiative grant signal to the next device.

FIG. 2 shows only a portion of the arbiter circuit 12 shown in FIG. 1 that is relevant to the present invention, including a D-type flip-flop 121, an exclusive N0II (ENOR) gate 122, and an eight Nr) Gate 124 is configured as shown. The circuit shown in FIG. 2 is a circuit for thinning out (inhibiting) the pasta lock signal BCLK as necessary, for example, when acquiring bus mastership for the terminal device 33. That is, as shown in FIG. 3, the D-type flip-flop 121 and ENO
The R gate 122 detects the rise or fall of the bus initiative granting signal BGR, and the bus clock signal BCLK is not output at the time of this rise or fall. The circuit shown in FIG. 2 is assumed to operate in response to the falling edge of clock signal CLK.

The operation of the system shown in FIG. 1 will be described below with reference to FIG.

The terminal device 33, device number: n, gains control of the bus, and the first device 31, device number: 0
Let us describe the case of writing data to .

The device 33 sends a bus mastership acquisition request signal BRQn to the arbiter circuit 1 via the bus 2 indicating that it wants to acquire bus mastership.
2 (FIG. 4(C)). The arbiter circuit 12 responds to the request signal BRQn with the bus initiative granting signal BGI? at the next clock CLK. Since it is known that the terminal device 33 cannot be reached within the clock that sends out the bus clock signal B, the arbiter circuit transmits the bus clock signal B as shown in FIG.
CLK is not output (FIG. 4(B) and FIG. 3).

When the BGR signal is accepted by the device 33, it outputs a bus initiative confirmation signal BAKn (FIG. 4(E)). At the same time, a multi-bit parallel bus address signal BA
x and multiple focus parallel bus data signals BDx are output to the bus (FIG. 4(H)).

(J)).

At the next clock, the request signal BRGn is turned off and the bus strobe signal BSTBn is output (Fig. 4 (C)).
, (F)). Further, the bus initiative granting signal BGR is turned off (FIG. 4(D)). In addition, the bus clock signal BCLK is inhibited in response to the falling edge of the signal BGR (see Fig. 4 (B
)).

On the other hand, due to the bus I lobe signal BSTBn,
The address signal BAx and the data signal BDx are sent to the first device 31, and when the device 31 completes reception, it outputs the bus data confirmation signal BDAKo (see FIG.
)) , data transmission and reception ends.

As a result, the signals BAKn and BST on the device 33 side
Bn is turned off, and the device 31 side also turns off the signal BDAKo at the next clock.

Transmission on bus 2 is partially prohibited (thinned) as described above.
This is done in synchronization with the bus clock signal BCLK.

In the above description, since the bus control signal BGRO is located far away from the arbiter circuit 12 and takes time to propagate, the bus clock signal BCLK' is inhibited pulse by pulse, and during that time the bus is controlled only by the propagation of the signal BGRO. Prevented the action from taking place. □Therefore, in cases where the number of devices increases and the propagation time of the BGR signal to the end device increases, the bus clock signal B
C'L K can be decimated by two pulses or more. Of course, the number of inhibited pulses can be arbitrarily determined depending on the interaction between the magnitude of the clock frequency and the propagation time delayed by the daisy chain due to the number of devices.

〔Effect of the invention〕

As described above, according to the present invention, bus initiative can be acquired without being limited by clock frequency.

By making it possible to obtain bus control without being subject to clock frequency limitations, the clock frequency can be set high and the bus transmission speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram as an embodiment of the present invention, and the second diagram is a diagram showing an embodiment of a part of the arbiter circuit shown in FIG. 1.
3 is a timing diagram showing the circuit operation of FIG. 2, and FIG. 4 is a timing diagram showing the operation of FIG. 1. (Explanation of symbols) ■...Processor board, 11...Microprocessor, 12...
・Arbiter circuit, 2...Bus, 3...Device section.

Claims (1)

[Claims] 1. When a plurality of devices are connected to a bus and the plurality of devices mutually transmit information via the bus in synchronization with a clock signal, a plurality of In a bus arbitration method in which a bus dominance grant signal connected in a daisy chain is given to a device to acquire bus dominance, a predetermined number of pulses of the clock signal are inhibited when a desired device acquires bus dominance. This bus arbitration method is characterized by the following: