JPH01116846U - - Google Patents
Info
- Publication number
- JPH01116846U JPH01116846U JP1113388U JP1113388U JPH01116846U JP H01116846 U JPH01116846 U JP H01116846U JP 1113388 U JP1113388 U JP 1113388U JP 1113388 U JP1113388 U JP 1113388U JP H01116846 U JPH01116846 U JP H01116846U
- Authority
- JP
- Japan
- Prior art keywords
- dma
- dma controller
- cycle
- detection means
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
Description
第１図は本考案のブロツク構成図、第２図は実
施例の構成を示す図、第３図はバス信号制御部の
動作フローチヤート、４図及び第５図はそれぞれ
動作を説明するためのタイミングチヤートである
。
１０…検出手段、２０…制御手段。
FIG. 1 is a block diagram of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment, FIG. 3 is an operation flowchart of the bus signal control section, and FIGS. 4 and 5 are diagrams for explaining the operation. This is a timing chart. 10...Detection means, 20...Control means.
Claims (1)
サイクルを検出するための検出手段と、上記検出
手段によつて上記複数のＤＭＡコントローラのＤ
ＭＡサイクルが衝突しないと検出されている場合
には、バス使用要求のあつたＤＭＡコントローラ
に許可信号を供給し、上記検出手段によつて上記
複数のＤＭＡコントローラのＤＭＡサイクルが衝
突すると検出された場合には、各ＤＭＡコントロ
ーラに予め割当てられた優先順位に従つて、優先
順位の高い側のＤＭＡコントローラから低い側の
ＤＭＡコントローラへ順次に１サイクルづつ遅ら
せて、許可信号を供給する制御手段とを具備した
ことを特徴とするＤＭＡコントローラ制御装置。 DMA of each of multiple DMA controllers
a detection means for detecting a cycle; and a detection means for detecting a cycle;
If it is detected that the MA cycles do not collide, a permission signal is supplied to the DMA controller that has made the bus use request, and if the detection means detects that the DMA cycles of the plurality of DMA controllers collide. The controller includes a control means for supplying a permission signal sequentially from a higher priority DMA controller to a lower priority DMA controller with a delay of one cycle in accordance with a priority assigned to each DMA controller in advance. A DMA controller control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1113388U JPH01116846U (en) | 1988-02-01 | 1988-02-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1113388U JPH01116846U (en) | 1988-02-01 | 1988-02-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01116846U true JPH01116846U (en) | 1989-08-07 |
Family
ID=31219413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1113388U Pending JPH01116846U (en) | 1988-02-01 | 1988-02-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01116846U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5621223A (en) * | 1979-07-30 | 1981-02-27 | Ibm | Cycle steal mechanism |
-
1988
- 1988-02-01 JP JP1113388U patent/JPH01116846U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5621223A (en) * | 1979-07-30 | 1981-02-27 | Ibm | Cycle steal mechanism |