JPS585804A - Process controller - Google Patents

Abstract

PURPOSE:To simplify the attachment/detachment of loop controllers to and from an on-line system by connecting the loop controllers with a common memory through serial data lines. CONSTITUTION:Loop controllers 10- are connected to an upper controller, a common memory 30, through respective serial transmission lines 20- independently. A data operation processing part 11 and a parallel/serial converting circuit 12 are built in each loop controller 10-. A common memory 30 makes it possible, if necessary, to execute the operation between respective loop controllers 10- through respective operation processing parts 11 in addition to the operation of individual loop controllers 10- or makes it possible to freely use an upper central operation processing part 41 for various operations and an upper transmitting controller 42.

Description

[Detailed description of the invention] TECHNICAL FIELD The present invention relates to a modification of Prussecomte cost-La.

As shown in Fig. 1 and Fig. 2, the conventional group w-k
Alternatively, a parallel path line 4 or a serial path line 5 of 1;N or NUH is used for data exchange between the higher-level central controller 2 and the higher-level transmission controller 3. However, the parallel bus line configuration shown in FIG. 1 has the following drawbacks.

First, when a certain loop controller 1 fails, there is a risk that data transmission of other normal loop controllers 1 will be stopped. In other words, because it is directly connected to path line 4, it may be due to a failure in the short circuit mode of the path driver or receiver)
If the pass line y4 is fixed at a low impedance, the pass line 4 will become unusable, and data communication will effectively become ineffective. Therefore, in order to avoid the above-mentioned problems, it is conceivable to make the pass line 4 redundant, but it is very expensive and also has problems in terms of space. It was. When performing online maintenance on the loop control and roller 1, it is necessary to attach and detach the modules without turning off the power, but for rounding that allows fins, it is necessary to turn the power switch on each module. It is necessary to devise a way to automatically turn off the power by setting it up and turning it off.p1
It has the drawbacks of high cost and increased storage space.

Next, number one! The nine serial path lines shown in the figure have the same drawbacks as the parallel path line 4 because the path structure is omitted. However, in this case, the number of pass lines 5 is small, so the number of pass lines 5 is relatively small.
Duplication is easy. 9. Since the path twin configuration is used, overconfidence cannot be established between three or more loop ports at the same time, so a separate time split port is required.

First, it is impossible to communicate a large amount of data at high speed, and the number of loop controllers 1 is limited to 91 units per unit, so if only the minimum necessary data is transmitted, the software It has become complicated and there are many problems.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to make it possible to perform loop control and to prevent failure of one loop controller from affecting other controllers. It also provides a single process controller that enables high-speed data communications. Another purpose is to make the communication between the loop controller and the central controller a one-to-one serial communication method, and to provide a shared memory so that the loop controller can communicate with both the controller and the controller. It provides a processor controller that can freely exchange all data between the controller and the upper controller.

1. Hereinafter, one embodiment of the present invention will be described with reference to the aS diagram and FIG. 4. Fig. 3 is a diagram showing the configuration of the Puda RyuScontora, and Fig. 4 is a diagram showing a specific example of the configuration of Fig. 3. In these figures, 10... is the loop controller.
Generally, 8 to 64 cars are seen at the same time, and this is the fourth
They are each independently connected to the shared memory S0 of the upper controller via serial transmission lines 2#. Each loop controller 210... Hatator operation processing unit (OPU) 11 and parallel-serial conversion circuit 1
It has 2 built-in. In addition to the individual loop controllers 510, the shared memo vJO executes calculations between the loop controllers 1 and 1 through the arithmetic processing unit 11, or is located at a higher level, as necessary. The central processing unit 41 for various calculations and the components 4j for upper-level transmission can be used freely on a time-sharing basis. tD, this shared memory 30 is used for each loop controller 10...
A serial-to-parallel converter circuit '3J' connected to the serial path 2-in-10 correspondingly, this converter circuit 11..., the central processing unit 41, and the controller for upper-level transmission. Random access memory (hereinafter referred to as RAM) I which is connected to the first parallel path line 31 connecting the 42 elements and can be shared by these elements.
A priority determination circuit that is connected to the conversion circuit 31, the second parallel path line 34 connecting the central processing unit 41, and the upper transmission controller 42 and determines the priority order of each element. J5 and shared memory control party-La 3
It consists of 6.

In addition, the central processing unit 41 and the upper-level transmission controller 4
2 is a parallel path twin 81.2 to speed up data exchange. :14 configuration, but of course these can also be serially transmitted.The arithmetic processing unit 11 of each loop controller 10... is responsible for data transmission with the host controller and for each loop. All data necessary for data transmission between controllers can be written to a predetermined memory address in a short time, and can also be written to other loop controllers 210 and 210.
... can be read from the 1mm MJJ when it is used up. In other words, the loop;
The arithmetic processing unit 11 of -L 10=-.
OM D) R as if executing the % store (8 0 RB) command.
AMJJ data can be used.

Next, the operation of the P4SEN controller configured as described above will be explained. First, an example in which the loop controller 4-210 writes data to the shared memory J0 will be described. The arithmetic processing unit 11 gives data, atsis, and a write flag to the parallel-to-serial conversion circuit 11, and after receiving these data, the parallel-to-serial conversion circuit 11 performs serial conversion and then stores the data in the shared memory S#. While transmitting at high speed to the serial-parallel converter circuit 31..., the circuit 11 is set in a wait state.The arithmetic processing unit 11 checks whether the serial converter circuit 11 is in an empty state or not. Since it is known in advance whether or not the data has been received, there is no need for a handshake.The serial-to-parallel conversion circuit J1 converts its own serial data into parallel data and sends only a flag to the priority determination circuit 35. Here, priority determination circuit S
5 from 7 lag Serial-to-parallel conversion circuit s1.
If it is determined that the request is from .

The serial-parallel conversion circuit 31 that received the permission signal converts the data into RA according to instructions from the shared memory controller 3C.
When writing to MJJ is completed, a write end signal is transmitted to the loop controller 10, and the parallel-to-serial conversion circuit 12 receives the write end signal and releases the wait of the arithmetic processing unit 11. When the serial conversion circuit 11 transmits data to the shared memory 10, it waits on the arithmetic processing section 11, but in this way, it marks the end of the transmission without setting it as a wait. Even if I let them know, I still feel sad, and
After writing the RAMJJK data in the serial-parallel conversion circuit 11, the data can be checked by reading the written data and transmitting this data to the loop controller 10 as a write end signal.

Next, a case in which the loop controller 10 reads data from the shared memory 80 will be described.

First, the calculation #& processing section 1 sets an address and a read flag in the parallel-serial conversion circuit 11. The parallel-to-serial conversion circuit 12 receives these data, converts them into serial data, and transmits them at high speed to the serial-to-parallel conversion circuit S1. At this time, the arithmetic processing unit 11 is set to wait. The serial-to-parallel conversion circuit 11 of the shared memory 10 converts the sent signal into parallel, and notifies the priority determination circuit JJ of the flag of the Daiken for which a read request is made from the loop controller 4-210. Here, the priority determination circuit 1J gives a permission signal to the bale for which priority determination has been made and to the serial-parallel conversion circuit J1. Upon receiving the permission signal, the serial-parallel conversion circuit 11 reads data from RAMJJ according to instructions from the shared memory controller J#, and after converting the read data from RAMJJ to serial data in the serial-parallel conversion circuit 31. , loop controller 10 serial conversion circuit 1
Transmit to j. With this ζ, parallel-serial conversion circuit 1
j receives the data from the mutual aid server 10, releases the weight, and sends the data to the arithmetic processing section 11 for processing.

Note that since a short signal such as 1 byte cannot generally be handled as analog hG data, the transmission/reception data for - times is set to have a length of 2 bytes or 4 bytes. At this time, if you pass one byte at a time, another loop may occur while the data is being written; when the client controller reads the data, a mismatch will occur, and to avoid this, a complicated circuit will be required.
Try to read and write data in units of data. , 31 and RAMjj are essentially configured into nine circuits each having the number of bits equivalent to one digit, such as 2 bytes or 4 bytes.

It should be noted that the present invention is not limited to the above embodiments.
In general, in a PC controller, if the shared message J# in the upper layer; When a failure occurs in .41,
It becomes impossible to transmit data from the loop controller 10 to the higher-level element, or to exchange data between the loop controllers 10 and 4. In order to solve this, 1. For example, the 51st
1. In the same figure, 10'.
... is a loop with a changeover switch; Jr is a self-check circuit in the host controller, Jl is a diagnostic circuit, and 4J is a selection circuit that selects the host transmission controller 41 based on the diagnostic output. It is. In the device shown in FIG. 1, the operation signals of the parity checkers of p1, 5, and M1j, the serial-to-parallel converter circuit 11, etc. are transmitted to the self-checker circuit 5F using OPυ, etc. The watchdog master check signal from the central processing unit 41 and the upper transmission controller 42 is taken in as an on@command and checked, and this check signal is sent to the diagnostic circuit aXK.
A loop controller 10' with a changeover switch and a selection circuit 41 are used to determine which system is defective based on the output of the switch and select the normal system based on the determination result.
send a signal to. Therefore, the controller 10' and the selection circuit 4J disconnect the unnecessary system and select and use the normal system based on the signal from the diagnostic circuit J1.

Note that since self-diagnosis by self-check is not necessarily universal, it is more desirable to perform manual switching as an auxiliary during switching from a higher-level element. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

As detailed above, according to the present invention, the loop punt field
Since the configuration is such that the loop controller and the shared loop are connected to the serial data line, it is convenient to make the loop controller online and detachable. Furthermore, since no pass line is formed, a failure of the loop controller will not spread to other devices, and high-speed overreliance of data is possible. This rounding and loop;
II! For this purpose, there is a roof; controller 1-
Since the data is owned by the central processing unit 41., the data can be used by other loop controllers, and the central processing unit 41. The loop controller can be simplified by writing all the data that may be used by the upper transmission controller into 8mm at high speed.

Since Moto 9 is equipped with shared memory as a high-level element, ``When one loop controller requests data from another loop controller, conventionally it interrupts 11 and requests the data directly.

10'0-υ10 has a very complicated arithmetic processing section (complicated configuration and data speed is uneven), but the software controller of the present invention has data in a shared memory. It is possible to maintain the independence of the loop controller including the above, and also to simplify the configuration.

Upper-level elements such as process sensor sole with ORT%;
If a computer receives data, it can be received from its own shared memory via direct data transmission. Provides a process controller that can increase nine data rates.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional process controller, FIG. 3 is a block diagram showing an embodiment of a process controller according to the present invention, and FIG. 4 is a block diagram of a conventional process controller.
FIG. 5 is a diagram showing a concrete example of the configuration of another example of the present invention. 1i・Proboscis・Roof; Ntora, 101...Loop with changeover switch; Ntora, 11...Calculation Jla11
part, 1t...parallel-serial conversion circuit %JO...
Shared memory, 37...Serial bar parallel 16 circuits, 77...RAM, jj...Priority determination circuit, J-
#, 4*・shared memory; component p-2, Jr... self-check circuit, 1a... diagnostic circuit, 41... central processing unit, 42... controller for upper transmission , 4
1...Selection circuit. Applicant's agent: Patent Attorney Tuling, Jiang'Wuliao No. 411 aSS

Claims (1)

[Claims] Nine independent loop controllers and upper R3/
) A shared memory that is placed on the roller side and stores the data required by each loop mint 4, and a serial twin that connects multiple loop controllers independently to this shared memory. A program is characterized in that a certain loop content sheet can freely read and use not only its own data but also the data of other loop content sheets from a shared memory. Four cesspunto is one.