JPH01209562A - Multi-cpu system - Google Patents

Abstract

PURPOSE:To obtain a multi-CPU system that can secure a satisfactory distance between CPUs by transferring serial data between the CPUs. CONSTITUTION:A data collecting CPU 3 outputs a control signal to a selection means 2 for selection of a CPU 1a, for example, among those CPU 1a-1c, etc., for monitor and control of each device. Thus necessary data are transmitted to and received from the CPU 1a. Then the CPU 3 sends the control signal to the means 2 again for selection of the next CPU 1b, for example, and performs the transfer of data to the CPU 1b. Such actions are repeated so that the transfer of data is possible with use of the serial signal in a multi-CPU system. As a result, any bus is not required for connection between the CPUs and each function block can be freely set.

Description

[Detailed Description of the Invention] [Summary] Regarding a multi-CPU system in which a plurality of computers operate independently and the CPUs of these computers are connected via, for example, a common memory, data transferred between the CPUs is The purpose of this system is to provide a system in which the distance between CPUs can be sufficiently long by using serial data.
The device is configured to have a selection means for selecting a PU, and a data aggregation CPU that controls the selection means and transmits and receives data in a serial format to and from the CPU group.

[Industrial application field]

In the present invention, a plurality of computers operate independently, and the CPUs of those computers share a common memory, for example.
The present invention relates to a multi-processor system connected via a sled, and particularly to a multi-CPU system in which a plurality of CPUs are connected using serial signals.

[Conventional technology]

Multiprocessor systems aimed at improving the processing power and reliability of computer systems include tightly coupled multiprocessor systems (TCMP), loosely coupled multiprocessor systems (LCMP), slave systems, and the like.

Tightly coupled systems are systems in which multiple processors access a common memory and peripheral devices, while loosely coupled systems are systems in which multiple processors each have independent local memory and peripheral devices, and communication between processors is through high-speed buses or communications. This method uses links. In addition, in a slave system, a peripheral processor, that is, a slave processor, exclusively owns an independent memory and peripheral device, and operates as a slave of a host processor, and the system is highly flexible and expandable.

A practical example of such a multiprocessor system is a multiple radio monitoring and control system. This system provides information such as the status of the line with the wireless station, information on the unmanned station station, i.e. information on power outages and other station buildings, and warnings in case the backup line is blocked and automatic rescue is not possible when the line goes down. This is a system that aggregates information regarding multiple wireless stations and monitors and controls the wireless stations.

FIG. 4 is a conventional block diagram showing a connection state between a plurality of CPUs that individually monitor and control each radio station or each device and a CPU for information aggregation in the above-mentioned monitoring and control system. In this figure, a CPU 51 is a CPU that plays a role of collecting information for intensive monitoring. CPU
-A32, CPU-B53, and CPU-C54...
- is for monitoring and controlling each radio station, etc. individually.

The CPU-A 32 to CPU-C 54, . . . have individual interfaces for individual wireless stations and devices, and therefore have individual firmware corresponding thereto. Although these individual firmwares are similar, there are differences due to, for example, differences in the number of lines and control methods.

Data from these CPUs 52 to 54 are stored in RAM 55 to
57 to the CPU 51 for data aggregation,
The signal is output to a central monitoring control device such as a display as a peripheral device. In other words, the aggregation CPU 51 is a CPU-A 32 and a CPU that correspond to individual stations, devices, and methods.
-B53, cpU-C54... It plays the role of an interface that unifies the format (to bring data from the central monitoring control device).In this system, the CPU 51, RAM55-57, RAM55-5
7 and the other CPOs 52 to 54 are connected to each other by bus, and data is input and output via the data bus.

[Problem to be solved by the invention]

In the conventional example of the supervisory control system shown in Fig. 4, the CPU and RAM
There is a bus connection between the two. Such a bus connection has a problem in that the connection distance cannot be made very long. That is, the maximum permissible length of a bus when connecting CPUs, or between a CPU and a RAM, etc., is determined by each standard. For example, the VME bus standard is 45 am, which is about a few tens of meters, and if the bus is extended beyond that, reliability will decrease and there will also be problems in terms of cost.

Therefore, in a multi-CPU system configured by bus connection between multiple CPUs using a common RAM, etc., as shown in the implementation example in Figure 5, the connection distance cannot be long, and the degree of freedom in mounting position is quite limited. That will happen.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a multi-CPU system in which the distance between CPUs can be sufficiently long by using serial data as data transferred between CPUs.

[Means to solve the problem]

The first principle block diagram of the multi-CPU system of the present invention is
As shown in the figure. In the same figure, multiple CPUs 1a, 1b) lc-b
...monitors wireless stations and equipment, etc. not shown, respectively.
Each device has its own firmware depending on its monitoring and control method. Although not shown, signals from each device etc. are input to these CPUs 1a to 1c through their input ports, and control signals etc. are outputted to each device etc. from their output ports.

The selection means 2 selects the plurality of CPUs 1a to lc'-...
・This is for selecting one of the following.

The data aggregation CPU 3 is a CPU for monitoring and controlling each device, etc.
This is for transmitting and receiving serial data between uta and IC% through the selection means 2, and outputting necessary data to a central monitoring and control device (not shown).

[For production]

In FIG. 1, the aggregation CPU 3 outputs a control signal to the selection means 2, and a plurality of CPUs 1a to 1 for monitoring and controlling each device, etc.
cs..., for example, the CPU 1a. The aggregation CPU 3 transmits and receives necessary data to and from the CPU 1a in serial format. After that, the CPU 3 sends a control signal to the selection means 2 again, and selects the next CPU, e.g.
1b is selected, and data is sent and received to and from cpuib. By repeating such operations, data transfer in a multi-CPU system can be performed using serial signals, and there is no need to use a bus to connect CPUs, etc.

〔Example〕

A block diagram of an embodiment of the present invention is shown in FIG. In the same figure, CP
UII is for aggregating monitoring and control data of each device, etc.
Inside it, data is stored using, for example, an HDLC procedure (High-
1 level Data Link Control P
There is an LS 112 for inputting and outputting according to the rocedure format.

A control signal for selecting one of the respective monitoring/controlling CPUs 16.22, . . . of each device is input from the data aggregation CPU II to the two selectors 13.14. The selector 13 outputs the CPU II output signal to drivers 15a and 15b.

..., 15p. For example, when the driver 15a is selected, the HDLC format data output from the LS 112 is input to the HDLC format data inside the CPU 16 via the driver 15a receiver 18a. Input to output LS117, CPU
The signal is transmitted to each device (not shown) via 16 output ports 21.

On the other hand, data from each device etc. is
Input to the input port of PU16.22.

For example, data input to the input port 20 of the CPU 16 is sent as serial data in HDLC format by the LSI 17 in the CPU 16 to the driver 19a receiver 16a1 selector 14 and the HDL in the CPU I.
The data is sent to a central monitoring and control device (not shown) via the C data input/output LS 112.

Next, the data transfer procedure in the multi-CPU system embodiment shown in FIG. 2 will be explained. Generally, there is a polling method as a method for controlling transmission rights in data communication. In this case, the control station (master station) listens to the dependent stations (slave stations) in turn to see if there is a transmission request, and if the dependent stations have data ready, they must send it to the control station or they will respond negatively. This method returns the information to the control station.

In this embodiment, after the CPU 1 outputs a control signal to the selector 13.14 and selects, for example, the CPU 16, a polling signal is input to the CPU 16 via the selector 13, the driver 15a, and the receiver 18a. CPU16
If there is data indicating a state change that is input to the input port 20 from a connection device (not shown), that data is input, and if not, a negative signal is input to the CPU II via the driver 19a, receiver 16a1 selector 14, and the data transfer is completed. let The CPU 1 sequentially polls the other CPUs 22, . . . by sending control signals to the selectors 13, 14. Furthermore, the CPU 11 can control the polling period of a CPU connected to a device or the like that sends a large amount of data to be shortened to reduce the waiting time for data transmission as much as possible.

In this embodiment, parallel data is converted into serial data using the HDLC procedure and transferred. This procedure is for transmitting bits through high-speed communication between computers. The frame, which is the unit of data transmission in this procedure, is
A 16-bit frame check sequence is included along with control data, transfer data, etc. between the start flag and end flag.

Cyclic redundancy code (CRC: Cyc) is used as a frame inspection method.
lic Redundancy Check), and extremely reliable data transmission can be achieved.

By using the HDLC format as the serial data format, transmission reliability can be improved and transmission can be extended over longer distances. In FIG. 2, data sending drivers 15a, 15b, . . . 15p118a118b
1. By using, for example, a Vll standard for . . . , the transmission distance can be made approximately 1 km, which is long enough for boat fishing. Therefore, the degree of freedom in mounting is greatly improved, and each CPU can be mounted in any manner as shown in FIG. In addition, in the case of a bus connection, the data bus,
Although the number of connections such as address buses increases, in the present invention, one CPU has two for sending and two for receiving, a total of 4.
All you need to do is connect the books.

In addition, the RAM 55 for data transfer in FIG. 4 of the conventional example
~57 is no longer necessary.

〔Effect of the invention〕

In a multi-CPU system, by transferring data between CPUs using serial data, there are no restrictions on the implementation of each CPU, and each functional block can be freely arranged. Furthermore, the number of connection lines is reduced, and a RAM for data transfer is no longer required, which is advantageous in terms of cost.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a multi-CPU system of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an implementation diagram of the embodiment, Fig. 4 is a block diagram of a conventional example of a multi-CPU system, FIG. 5 is an implementation diagram of a conventional example. 11... CPU for data aggregation. 16.22...cp12.1 for monitoring and controlling each device, etc.
7.23... LSI for inputting and outputting data in HDLc format, 13.15... Selector.

Claims (1)

[Claims] A CPU group (1) for controlling each of a plurality of devices, a selection means (2) for selecting any one CPU of the CPU group (1), and a CPU for controlling the selection means (2). , a multi-CPU system comprising a data aggregation CPU (3) that transmits and receives data in a serial format to and from the CPU group (1).