JPH0619838A - Optical back plane - Google Patents

Abstract

PURPOSE:To improve the extensiveness of a multi-microprocessor system. CONSTITUTION:Opto-electric tranducers 941-94N tranducing a light signal which respective microprocessor boards 201-20N transmit into an electric signal and outputting it, a transmission control part 92 monitoring whether a collision occurs in transmission data or not, transferring all data which the respective microprocessor boards 201-20N transmit to the microprocessor boards 201-20N when the collision does not occur, transferring all data which the microprocessor board with the highest priority transmits to the microprocessor boards 201-20N and abolishing data which the other microprocessor boards transmit when the collision occurs, and electric/optic converters 931-93N converting the electric signal transferred from the transfer control part 92 into the light signal and outputting it to the respective microprocessor boards are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backplane,
In particular, it relates to an optical backplane for optical interconnection between a plurality of microprocessor boards.

[0002]

2. Description of the Related Art At present, with the increasing demand for more multifunctional and faster processing for computer systems, the number of multi-microprocessor systems capable of connecting a plurality of microprocessor boards and distributing the processing is increasing.

Conventionally, an electrical backplane 10 for transferring K-bit data in parallel as shown in FIG. 12 has been used for connection between microprocessor boards. The electric backplane 10 includes a data bus 11 made up of K electric signal lines for performing parallel transfer of data exchanged between the microprocessor boards, and an electric signal line M for designating a microprocessor board to which data is to be transferred. An address bus 12 composed of a book, an electric signal line 13 for acquiring a bus use right for determining which microprocessor board uses a data bus and an address bus, and a power supply line for supplying power to each microprocessor board. And a power line 14. As shown in FIG. 13, each of the microprocessor boards 201 to 20N includes a data bus 11, an address bus 12, an address bus usage right acquisition signal line 13, and a power line 14 of the electrical backplane 10 via connectors 211 to 21N, respectively. Connected to everything.

Each microprocessor board 201-20
The Ns are logically connected by an address space whose range is determined by the address bus 12 of the electrical backplane 10 from 0 to 2 ^M-1 . The address space 30 is shown in FIG.
A configuration example of is shown. As shown in FIG.
Are allocated to the address area 301 allocated to the microprocessor board 201, the address area 302 allocated to the microprocessor board 202, the address area 303 allocated to the microprocessor board 203, and the microprocessor board 20N-1. Address area 30N-1 and the address area 30 assigned to the microprocessor board 20N
It is occupied by N. Thus, in the conventional electric backplane, each microprocessor board is logically connected by fixedly allocating a certain area in the address space.

Each of the microprocessor boards 201 to 20
In order to transfer data between N, first, the microprocessor board that transmits data outputs a signal for acquiring the right to use the data bus and address bus, and after acquiring the right to use these buses, the data is transmitted to the address bus. The address of the partner microprocessor board is output, and the transmission data is output to the data bus. As an example thereof, FIG. 15 shows the state of signals output from the microprocessor board 201 when transmitting data from the microprocessor board 201 to the microprocessor board 202. The microprocessor board 201 outputs the bus use right acquisition signal 41, and at the time 42 when the use right of the data bus 11 and the address bus 12 is acquired, the address bus 12 receives the address of the microprocessor board 202 of the data transmission partner. Address 302 in area 302
a is output, and the transmission data 43 is output to the data bus 11. Thus, in the conventional electric backplane, each microprocessor board transfers data on a one-to-one basis.

[0006]

By the way, in the conventional multi-microprocessor system using the above-mentioned electric backplane, there are problems in system extensibility and data transfer.

As an example, FIG. 16 shows a case where a microprocessor board is newly added to a certain multi-microprocessor system to add a function. In the figure, the microprocessor boards 201 to 20N are the microprocessor boards shown in FIG. 13, and the microprocessor board 20N + 1 is a microprocessor board newly added to add a function. The address space of this multi-microprocessor system is shown in FIG. Figure 1
7, the address space 61 is allotted to the existing microprocessor boards 201 to 20N,
The area 30N + 1 required by the newly added microprocessor board 20N + 1 cannot be allocated within the range of the address space 61. Therefore, it is not possible to logically connect the microprocessor boards 201 to 20N and the newly added microprocessor board 20N + 1, and it is possible to save data between the microprocessor boards 201 to 20N and the newly added microprocessor board 20N + 1. I can not deliver.

As described above, in the conventional electric backplane, it seems that it is easy to expand the system by enlarging the size of the backplane and further increasing the number of connectors, but this is only physical. Since it is a simple extension, it is not possible to extend the system beyond the address space required for normal data transfer.

Next, FIG. 18 shows a case where a microprocessor board is improved to improve the function of a certain multi-microprocessor system. In the figure, a microprocessor board 201 and a microprocessor board 2
Reference numerals 03 to 20N denote microprocessor boards that form the multi-microprocessor system shown in FIG.
The microprocessor board 202a is an improved microprocessor board for improving performance. The address space of this multi-microprocessor system is shown in FIG. In FIG. 19, the address area 8 required by the improved microprocessor board 202a for improving the performance is shown.
2 is wider than before the improvement, the area 83 is overlapped with the area 301 allocated to the adjacent microprocessor board 201, and the area allocated to the microprocessor board 203. Three
The area 84 overlaps with area 03. Therefore, when a microprocessor board other than the microprocessor board 202a and the microprocessor board 201 sends data to an address within the area 83 where the address areas overlap, the microprocessor board 202
Since both a and the microprocessor board 201 receive data, normal data transfer cannot be performed. Further, when a microprocessor board other than the microprocessor board 202a and the microprocessor board 203 sends data to an address in the area 84 where the address areas overlap, both the microprocessor board 202a and the microprocessor board 203 receive the data. I am unable to deliver normal data because it is lost.

As described above, in the conventional multi-microprocessor system using the electric backplane,
Even when a part of the microprocessor boards constituting the system is improved in order to improve the performance, normal data transfer cannot be performed unless the address space of the existing system is changed.

Further, as described above, in the conventional electric backplane, each microprocessor board has a one-to-one correspondence.
Since the data is delivered by the microprocessor, even when a certain microprocessor board transmits the same content data to all the microprocessor boards, the data delivery operation as shown in FIG. 14 is performed by all the other microprocessor boards. It is inefficient because it must be done for the number of sheets.

The object of the present invention is to solve the above-mentioned drawbacks of the prior art, to provide excellent expandability of a multi-microprocessor system, and to extend between all the microprocessor boards constituting the system even when the system is expanded. It is to provide a new backplane that can transfer data normally.

[0013]

In order to achieve the above object, an optical backplane of the present invention comprises a signal line for transmitting data in series between a plurality of microprocessor boards constituting a multi-microprocessor system, Whether an optical / electrical converter that converts an optical signal transmitted by each microprocessor board into an electric signal and outputs the electric signal to the signal line and a transmission data of each microprocessor board in the middle of the optical transmission line have collided or not collided? If there is no collision, transfer all data sent by each microprocessor board to all microprocessor boards as they are, and if a collision occurs,
Transfers data sent by the highest priority microprocessor board to all microprocessor boards,
It is provided with a transmission control unit that discards the data transmitted by the other microprocessor boards, and an electric / optical converter that converts the electric signal transferred from the transmission control unit into an optical signal and outputs the optical signal to each microprocessor board. Or the number of all microprocessor boards that transmit the signals transmitted by each microprocessor board and the optical transmission path for serially transmitting data between the multiple microprocessor boards that make up the multi-microprocessor system. And an optical branching device for branching for more than one minute.

[0014]

The optical backplane of the present invention employs a transmission path structure for serially transmitting data instead of a bus structure for parallelly transferring data exchanged between microprocessor boards. Therefore, each microprocessor board detects if the data it has sent collides with the data sent by another microprocessor board by monitoring the content of the data received from the optical backplane, and When there is a data collision, the function to retransmit the same frame is provided so that the data can be delivered normally without affecting the existing address space even when the multi-microprocessor system is expanded. It can be carried out. Since it is possible to easily provide the microprocessor board with the above function by changing the program, etc., a high-performance multi-microprocessor system using the existing microprocessor board is realized by using the optical backplane of the present invention. be able to.

[0015]

EXAMPLES Next, examples of the present invention will be described.

[Embodiment 1] FIG. 1 is a diagram showing a first embodiment of the present invention, showing a connection form between an optical backplane 90 and N microprocessor boards 201 to 20N. The optical backplane 90 converts signal lines 921 to 92N and 92R for serially transmitting data between the microprocessor boards 201 to 20N and optical signals transmitted by the respective microprocessor boards 201 to 20N into electric signals. The optical / electrical (O / E) converters 941 to 94N output to the signal lines 921 to 92N and the signal lines 921 to 92N and the signal lines 92R are relayed and the transmission data of the respective microprocessor boards 201 to 20N collide. Monitor whether or not any of the microprocessor boards 201 to 20 has occurred if no collision occurs.
All the data transmitted by N are transferred to all the microprocessor boards 201 to 20N as they are, and when a collision occurs, the data transmitted by the microprocessor board with the highest priority is transferred to all the microprocessor boards 2
01-20N, and discards the data transmitted by the other microprocessor boards, and a transmission control unit 91, and an electric signal transferred from the transmission control unit 91 is converted into an optical signal, and each microprocessor board 201-20N To an electric / optical (E / O) converter 931 to 93N and a power line 95 for supplying electric power to each of the microprocessor boards 201 to 20N. E / O
Converters 931 to 93N and O / E converters 941 to 94N
Are arranged in a set corresponding to each of the microprocessor boards 201 to 20N, and optical connectors 961 to 96N are provided for each set. In addition, the power connector 21 is provided adjacent to each of the optical connectors 961 to 96N.
1 to 21N are arranged. In practice, the number of optical transmission lines, O / E and E / O converters, connectors, etc. is set larger than the initial number of microprocessor boards so that microprocessor boards can be added later for system expansion.

Microprocessor boards 201-20N interconnected by an optical backplane 90 are shown in FIG.
The internal circuit 105 including the main processor, the access control unit 104 for controlling the communication with the other microprocessor board, and the data for the other microprocessor board are serially transmitted from the other microprocessor board as shown in FIG. And a data serial / parallel conversion circuit 101 for converting the reception data of the above into parallel data. The data serial-parallel conversion circuit 101 is an E / O converter 102 connected to the optical connectors 961 to 96N of the optical backplane 90.
It is also connected to the O / E converter 103. Each of the microprocessor boards 201 to 20 configured in this way
N serially transmits data for another microprocessor board. Further, at the time of transmission, each of the microprocessor boards 201 to 20N transmits serial data addressed to the other microprocessor boards in frame units of a fixed length. The structure of the frame is shown in FIG. In FIG. 3, 111 is a frame start display area, 112 is an L-bit transmission destination address display area, 113 is an L-bit transmission source address display area, 114 is a data area, and 115.
Is a frame end display area. 112 and 113 are 2
It can represent ^L addresses. Each of the microprocessor boards 201 to 20N receives from the optical backplane 90 whether or not the data transmitted by itself collides with the data transmitted by another microprocessor board and is discarded by the transmission control unit 91 inside the optical backplane 90. Detect by observing the contents of the frame.

As shown in FIG. 1, in the optical backplane 90 of this embodiment, there is no signal line for designating the microprocessor board of the data transfer partner such as the address bus 12 in the conventional electric backplane. Therefore, the address of the microprocessor board 201 is 1, the address of the microprocessor board 202 is 2, the address of the microprocessor board 203 is 3, the address of the microprocessor board 20N is N, and so on. A static address. Thus, in the optical backplane 90 of this embodiment, each microprocessor board is logically connected by assigning a single theoretical address to each microprocessor board. In addition, since the addresses assigned to each microprocessor board are logical, all microprocessor boards are assigned to one group, and one address is assigned to that group. It is also possible to specify.

At the time of data transfer, the microprocessor board transmitting data writes its address in the address display area 113 of the transmission source and the address of the microprocessor board of the transmission destination in the address display area 112 of the transmission destination. Send the embedded frame. Then, the microprocessor board that has transmitted the data receives the address display area 113 of the transmission source and the address display area 1 of the transmission partner of the frame received from the optical backplane 90.
It is detected by monitoring the contents of 12 whether the transmitted frame is transferred to the microprocessor board of the transmission partner or discarded by the transmission control unit 91 inside the optical backplane 90, and if it is discarded, the same frame is retransmitted. To do.

As an example, the microprocessor board 2
FIG. 4 shows a frame output from the microprocessor board 201 when transmitting data from 01 to the microprocessor board 202. In the figure, the microprocessor board 2 is displayed in the address display area 112 of the transmission partner.
The address 2 of 02 is written, and the address 1 of the microprocessor board 201 is written in the address display area 113 of the transmission source. The microprocessor board 201 transmits this frame, then monitors the frame received from the optical backplane 90, and the address display area of the source of the frame received from the optical backplane 90 is 1 and the address display of the transmission partner is displayed. If the area is 2, it is considered that the transmitted frame has been transferred to the microprocessor board 202 of the transmission partner, and the address display area of the transmission source is not 1 or the address display area of the transmission partner is 2.
If not, the transmitted frame is the optical backplane 9
The same frame is retransmitted by assuming that the same frame has been discarded by the transmission control unit 91 inside 0.

Next, the system expandability of the multi-microprocessor system constructed by using the optical backplane 90 will be described.

FIG. 5 shows a case where another microprocessor board is newly added to the existing multi-microprocessor system to add a function. In the figure, microprocessor boards 201 to 20N are microprocessor boards constituting the multi-microprocessor system shown in FIG.
+1 is a microprocessor board newly added to add a function. Here, the microprocessor board 20
N + 1 is assigned to the N + 1 logical address.
The total number Y of addresses assigned to the microprocessor boards 201 to 20N + 1 is the address display area 112 of the L-bit transmission partner of the frame output from each of the microprocessor boards 201 to 20N and the address display area 113 of the L-bit transmission source. If there are less than 2 ^L addresses that can be represented by, that is, if Y ≦ 2 ^L , the microprocessor board 201 is written by writing N + 1 to the address display area 112 of the transmission partner or the address display area 113 of the transmission source. Data can be exchanged between .about.20N and the microprocessor board 20N + 1. In addition, the microprocessor board 201
The total number Y of addresses allocated to ˜20N + 1 can be represented by 2 ^L of the address display area 112 of the L-bit transmission partner of the frame output from each microprocessor board and the address display area 113 of the L-bit transmission source. If there are more addresses than Y, that is, Y> 2 ^L , as shown in FIG. 6, the address display area 11 of the transmission partner of the frame output by each microprocessor board is displayed.
2 and the address display area 113 of the transmission source are set to L + p bits, and L + p is set to a value satisfying Y ≦ 2 ^{L + p} , thereby writing N + 1 to the address display area 112 of the transmission partner or the address display area 112 of the transmission source. By
Data can be exchanged between the microprocessor boards 201 to 20N and the microprocessor board 20N + 1.

FIG. 7 shows a case where some of the microprocessor boards are improved to improve the functions of the existing multi-microprocessor system. In the figure, a microprocessor board 201 and microprocessor boards 203 to 20N are microprocessor boards constituting the multi-microprocessor system shown in FIG. 1, and a microprocessor board 202a is an improved microprocessor board for improving performance. . In this case, if the address of the microprocessor board 202a is set to 2 similarly to the address of the microprocessor board 202 before improvement, data can be exchanged in the same manner as before the improvement of the microprocessor board 202.

As described above, in the optical backplane 90 of this embodiment, all the microprocessor boards are grouped into one group and one address is assigned to the group, so that all the microprocessor boards are assigned one address. It is also possible to specify. Therefore, when a certain microprocessor board transmits the data of the same content to all the other microprocessor boards, one type of frame is written by writing the addresses representing all the above-mentioned microprocessor boards in the address display area of the transmission partner. It is very efficient to send once.

[Second Embodiment] FIG. 8 shows a second embodiment of the present invention. The optical backplane 100 shown in the figure has optical transmission lines 971 to 97N and 981 for serially transmitting data among a plurality of microprocessor boards 201 to 20N that form a microprocessor system.
~ 98N and each microprocessor board 201-20
Signals (optical signals) from N are branched into a number equal to or more than the number of all microprocessor boards, and optical transmission lines 981 to 9
Optical branching device 92 for sending to 8N and power line 9 for supplying power to each microprocessor board 201 to 20N
And 5 are provided. Optical connectors 961 to 96N are provided for each set of input and output ends of the optical transmission line.
Power connectors 211 to 21N are arranged adjacent to the optical connectors 961 to 96N. Actually, the number of optical transmission lines, connectors, etc. is set larger than the initial number of microprocessor boards so that a microprocessor board can be added later for system expansion.

The optical backplane 1 configured as described above
00, each microprocessor board 201-
The optical signal transmitted by the 20N is branched by the optical branching device 91 and transferred to all the microprocessor boards 201 to 20N.

Microprocessor boards 201-20N interconnected by an optical backplane 100 include internal circuits 10 that include a main processor 106, as shown in FIG.
5, an access control unit 104 for controlling communication with other microprocessor boards, and data for other microprocessor boards are serially transmitted, and reception data from other microprocessor boards is converted into parallel data. The data serial-parallel conversion circuit 101 for converting is provided.
The internal circuit 105 has a main memory 107 and a communication control processor 109 in addition to the main processor 106, and these are connected to the access control unit 104 via a processor board bus 108. Data serial-parallel conversion circuit 10
1 is the optical connectors 961 to 96 of the optical backplane 90.
It is connected to the O / E converter 102 and the E / O converter 103 which are connected to N. Each of the microprocessor boards 201 to 20N configured as described above serially transmits data for another microprocessor board.
In addition, each microprocessor board 201 to
The 20N transmits serial data addressed to another microprocessor board in units of frames of a fixed length. That frame
The configuration of the system is the same as in FIG.

As shown in FIG. 8, in the optical backplane 100 of this embodiment, the conventional electrical backplane 1 is used.
There is no signal line designating the microprocessor board of the data transfer partner such as the address bus 12 at 0. Therefore, even when a microprocessor system is configured using the optical backplane 100, each of the microprocessor boards 201 to 20 is similar to the first embodiment.
A single logical address is assigned to N to logically connect the respective microprocessor boards 201 to 20N. At the time of data transfer, the microprocessor board transmitting the data writes its own address in the address display area 113 of the transmission source, and the address of the microprocessor board of the transmission destination is displayed in the address display area 11 of the transmission destination.
The frame written in 2 is transmitted. The microprocessor board that transmitted the data is the optical backplane 10
Address display area 1 of the source of the frame received from 0
13 and the contents of the address display area 112 of the transmission partner are detected to detect whether the transmitted frame is transferred to the microprocessor board of the transmission partner or collides with the data transmitted by another microprocessor board, In case of collision, the same frame is retransmitted.

As an example, the microprocessor board 2
A data transfer method for transmitting data from 01 to the microprocessor board 202 will be described. The structure of the frame output from the microprocessor board 201 is the same as that shown in FIG. Microprocessor board 201
Transmits a frame and then the optical backplane 10
Optical backplane 1 monitors frames received from 0
The address display area 113 of the transmission source of the frame received from 00 is 1 and the address display area 1 of the transmission partner is 1.
If 12 is 2, it is considered that the transmitted frame has been transferred to the partner microprocessor board, otherwise, the transmitted frame collides with data sent by another microprocessor board and a normal data frame is transferred. The same frame is retransmitted, assuming that it did not exist.

Next, the system expandability of the multi-microprocessor system constructed by using the optical backplane 100 will be described.

FIG. 10 shows a case where another microprocessor board is newly added to the existing multi-microprocessor system to add a function. In the figure, microprocessor boards 201 to 20N are microprocessor boards constituting the multi-microprocessor system shown in FIG.
N + 1 is a microprocessor board newly added to add a function. Where microprocessor board 2
N + 1 is assigned to the logical address of 0N + 1. The total number Y of addresses assigned to the microprocessor boards 201 to 20N + 1 is the address display area 112 of the L-bit transmission partner of the frame output from each of the microprocessor boards 201 to 20N and the address display area 113 of the L-bit transmission source. Can be represented by 2
^{If the} number of addresses is smaller than ^L , that is, if Y ≦ 2 ^L , N + 1 is written in the address display area 112 of the transmission partner or the address display area 113 of the transmission source, so that the microprocessor boards 201 to 20N and the microprocessor board Data can be exchanged between 20N + 1. Also, the total number Y of addresses assigned to the microprocessor boards 201 to 20N + 1 is Y.
Is the address display area 112 of the L-bit transmission partner of the frame output from each microprocessor board, and L
When there are more than 2 ^L addresses that can be represented by the address display area 113 of the transmission source of the bits, that is, Y>
In the case of 2 ^L , as in the first embodiment, as shown in FIG. 6, the address display area 112 of the transmission partner of the frame output from each microprocessor board and the address display area 113 of the transmission source are set to L + p bits, L + p is Y ≤ 2
^A value that satisfies ^{L + p} , and the address display area 11
2 or N + 1 in the address display area 112 of the transmission source, the microprocessor boards 201 to 20
Data can be exchanged between N and the microprocessor board 20N + 1.

FIG. 11 shows a case where some of the microprocessor boards are improved to improve the functions of the existing multi-microprocessor system. In the figure,
The microprocessor board 201 and the microprocessor boards 203 to 20N are microprocessor boards constituting the multi-microprocessor system shown in FIG. 8, and the microprocessor board 202a is an improved microprocessor board for improving performance. In this case, if the address of the microprocessor board 202a is set to 2 similarly to the address of the microprocessor board 202 before improvement, data can be exchanged in the same manner as before the improvement of the microprocessor board 202.

Also in this optical backplane 100, it is possible to designate all microprocessor boards by one address by assigning one address to each group as a group of all microprocessor boards. is there. Therefore, when a certain microprocessor board transmits the data of the same content to all the other microprocessor boards, by writing the addresses representing all the above-mentioned microprocessor boards in the address display area 112 of the transmission partner,
It is very efficient to transmit one type of frame once.

[0034]

In summary, the optical backplane of the present invention has excellent expandability in a multi-microprocessor system, and when the system is expanded, data can be normally transferred between all the microprocessor boards constituting the system. It has an excellent effect that it can be done efficiently.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multi-microprocessor system showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing microprocessor boards interconnected by the optical backplane of FIG.

FIG. 3 is a diagram showing a configuration example of a frame transmitted by a microprocessor board interconnected by an optical backplane of the present invention.

FIG. 4 is a diagram showing a configuration example of a frame transmitted by a microprocessor board interconnected by an optical backplane of the present invention.

5 is a configuration diagram showing a case where a microprocessor board is newly added for adding a function to the multi-microprocessor system shown in FIG.

FIG. 6 is a diagram showing a configuration example of a frame transmitted by a microprocessor board interconnected by an optical backplane of the present invention.

FIG. 7 is a configuration diagram showing a case where some of the microprocessor boards are improved in order to improve the functions of the multi-microprocessor system shown in FIG.

FIG. 8 is a configuration diagram of a multi-microprocessor system showing a second embodiment of the present invention.

9 is a block diagram showing a microprocessor board interconnected by the optical backplane of FIG. 8. FIG.

10 is a configuration diagram showing a case where a microprocessor board is newly added to the multi-microprocessor system shown in FIG. 8 for adding a function.

11 is a configuration diagram showing a case where some of the microprocessor boards are improved to improve the functions of the multi-microprocessor system shown in FIG.

FIG. 12 is a configuration diagram showing a conventional electric backplane.

FIG. 13 is a configuration diagram of a multi-microprocessor system configured using a conventional electric backplane.

14 is a diagram showing an example of an address space of the multi-microprocessor system shown in FIG.

FIG. 15 is a diagram showing a timing chart for explaining a data delivery method between the respective microprocessor boards in the multi-microprocessor system configured by using the conventional electric backplane.

16 is a configuration diagram showing a case where a microprocessor board is newly added for adding a function to the multi-microprocessor system shown in FIG.

17 is a diagram showing an example of an address space of the multi-microprocessor system shown in FIG.

18 is a configuration diagram showing a case where some of the microprocessor boards are improved to improve the functions of the multi-microprocessor system shown in FIG.

19 is a diagram showing an example of an address space of the multi-microprocessor system shown in FIG.

[Explanation of symbols]

90 Optical Backplane 91 Transmission Control Unit 92 Optical Divider 100 Optical Backplane 921 to 92N + 1 Signal Line 92R Signal Line 931 to 93N + 1 Electric / Optical (E / O) Converter 941 to 94N + 1 Optical / Electric (O / E) Converter 971 to 97N + 1 Optical transmission line 981 to 98N + 1 Optical transmission line 201 to 20N Microprocessor board 20N + 1 Microprocessor added to add system function 202a Microprocessor improved to improve system function

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumiki Sone 5-1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture, Hitachi Cable Ltd. Optro System Research Laboratories (72) Inventor Matsuaki Terada Aso-ku, Kawasaki City, Kanagawa Prefecture Ozenji 1099 Stock Company Hitachi Systems Development Laboratory

Claims (2)

[Claims] 1. A signal line for serially transmitting data between a plurality of microprocessor boards forming a multi-microprocessor system, and an optical signal for converting an optical signal transmitted by each microprocessor board into an electric signal. To the optical / electrical converter that outputs to and the transmission data of each microprocessor board in the middle of the above-mentioned signal line, whether or not collision has occurred, and if collision does not occur, all data transmitted by each microprocessor board To all microprocessor boards, and if a collision occurs, transfer the data sent by the highest priority microprocessor board to all microprocessor boards and the data sent by the other microprocessor boards. Transmission control unit to be discarded and the transmission control unit An optical backplane comprising: an electric / optical converter that converts an electric signal transferred from the optical signal into an optical signal and outputs the optical signal to each microprocessor board. 2. An optical transmission line for serially transmitting data between a plurality of microprocessor boards constituting a multi-microprocessor system, and signals transmitted by the respective microprocessor boards for all the microprocessor boards. An optical backplane, comprising: an optical branching device that branches as described above.