CN111324563A - A combined system and method of PCIe device physical lane - Google Patents

A combined system and method of PCIe device physical lane Download PDF

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CN111324563A
CN111324563A CN202010108880.XA CN202010108880A CN111324563A CN 111324563 A CN111324563 A CN 111324563A CN 202010108880 A CN202010108880 A CN 202010108880A CN 111324563 A CN111324563 A CN 111324563A
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孙一心
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract

本发明公开了一种PCIe设备物理lane的组合系统，包括上位机和控制装置。上位机根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息至控制装置；控制装置根据lane配置信息，将非标准PCIe接口和标准PCIe接口的lane进行组合，以实现两接口的通信连接。可见，本申请可实现非标准PCIe接口和标准PCIe接口的lane自由组合，从而有利于自定义的PCIe接口连接设备的开发设计。本发明还公开了一种PCIe设备物理lane的组合方法，与上述组合系统具有相同的有益效果。

Figure 202010108880

The invention discloses a combined system of PCIe equipment physical lanes, which includes an upper computer and a control device. The host computer generates lane configuration information representing the lane combination mode between the two interfaces to the control device according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface; the control device combines the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information. The lanes of the interface are combined to realize the communication connection between the two interfaces. It can be seen that the present application can realize the free combination of lanes of non-standard PCIe interfaces and standard PCIe interfaces, thereby facilitating the development and design of customized PCIe interface connection devices. The invention also discloses a method for combining physical lanes of PCIe devices, which has the same beneficial effects as the above combined system.

Figure 202010108880

Description

一种PCIe设备物理lane的组合系统及方法A combined system and method of PCIe device physical lane

技术领域technical field

本发明涉及PCIe设备领域，特别是涉及一种PCIe设备物理lane的组合系统及方法。The present invention relates to the field of PCIe devices, in particular to a combined system and method for physical lanes of PCIe devices.

背景技术Background technique

PCIe(Peripheral Component Interconnect Express，外围元件快速互连)是一种高速串行计算机扩展总线标准。目前，由于PCIe总线具有速率高、容错率好、拓展方便等优势，服务器系统大都通过PCIe总线来拓展外设。现有技术中，PCIe设备的接口顺序和物理形态通常是标准的，但在服务器系统设计PCIe接口时，有时候会存在非标准插槽的情况，如果此情况要连接标准接口的PCIe设备，通常采用的技术手段是通过转接卡进行接口转换。但是，在这种连接方式下，非标准PCIe接口和标准PCIe接口的物理lane(链路)组合方式是固定的，从而不利于自定义的PCIe接口连接设备的开发设计。PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. At present, because the PCIe bus has the advantages of high speed, good fault tolerance, and easy expansion, most server systems use the PCIe bus to expand peripherals. In the prior art, the interface sequence and physical form of PCIe devices are usually standard, but when designing a PCIe interface in a server system, there are sometimes non-standard slots. The technical means used is to perform interface conversion through a riser card. However, in this connection mode, the physical lane (link) combination mode of the non-standard PCIe interface and the standard PCIe interface is fixed, which is not conducive to the development and design of a custom PCIe interface connection device.

因此，如何提供一种解决上述技术问题的方案是本领域的技术人员目前需要解决的问题。Therefore, how to provide a solution to the above technical problem is a problem that those skilled in the art need to solve at present.

发明内容SUMMARY OF THE INVENTION

本发明的目的是提供一种PCIe设备物理lane的组合系统及方法，可实现非标准PCIe接口和标准PCIe接口的lane自由组合，从而有利于自定义的PCIe接口连接设备的开发设计。The purpose of the present invention is to provide a system and method for combining physical lanes of PCIe devices, which can realize the free combination of lanes of non-standard PCIe interfaces and standard PCIe interfaces, thereby facilitating the development and design of customized PCIe interface connection devices.

为解决上述技术问题，本发明提供了一种PCIe设备物理lane的组合系统，包括：In order to solve the above technical problems, the present invention provides a combination system of PCIe device physical lanes, including:

上位机，用于根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息；The upper computer is used to generate lane configuration information representing the lane combination mode between the two interfaces according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface;

分别与所述非标准PCIe接口、所述标准PCIe接口及所述上位机连接的控制装置，用于根据所述lane配置信息，将所述非标准PCIe接口和所述标准PCIe接口的lane进行组合，以实现两接口的通信连接。A control device connected to the non-standard PCIe interface, the standard PCIe interface and the host computer respectively, for combining the lanes of the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information , in order to realize the communication connection between the two interfaces.

优选地，所述上位机具体用于：Preferably, the host computer is specifically used for:

根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，按照所述非标准PCIe接口的lane顺序，依次生成表征将所述非标准PCIe接口的第n条lane配置到所述标准PCIe接口的第m条lane的配置数据包；其中，n、m均为正整数；According to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface, and according to the lane order of the non-standard PCIe interface, sequentially generate the lanes representing the configuration of the nth lane of the non-standard PCIe interface to the standard PCIe interface. The configuration data packet of the mth lane; among them, n and m are both positive integers;

则所述控制装置具体用于根据依次生成的配置数据包，对应将所述非标准PCIe接口的第n条lane配置到所述标准PCIe接口的第m条lane，以完成所述非标准PCIe接口和所述标准PCIe接口的lane组合。Then the control device is specifically configured to configure the n-th lane of the non-standard PCIe interface to the m-th lane of the standard PCIe interface according to the configuration data packets generated in sequence, so as to complete the non-standard PCIe interface. and the lane combination of the standard PCIe interface.

优选地，所述控制装置包括：Preferably, the control device includes:

与所述上位机连接的单片机，用于接收所述上位机生成的lane配置信息，并将所述lane配置信息传输至FPGA；The single-chip microcomputer connected with the host computer is used to receive the lane configuration information generated by the host computer, and transmit the lane configuration information to the FPGA;

分别与所述非标准PCIe接口和所述标准PCIe接口连接的FPGA，用于根据所述lane配置信息，将所述非标准PCIe接口和所述标准PCIe接口的lane进行组合，以实现两接口的通信连接。The FPGAs respectively connected with the non-standard PCIe interface and the standard PCIe interface are used to combine the lanes of the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information, so as to realize the two interfaces. communication connection.

优选地，所述上位机还用于在发送所述lane配置信息之前，向所述单片机发送表征开始标志的数据包，并在发送完所述lane配置信息之后，向所述单片机发送表征结束标志的数据包；Preferably, the host computer is further configured to send a data packet representing a start flag to the single-chip microcomputer before sending the lane configuration information, and after sending the lane configuration information, send a characterizing end flag to the single-chip microcomputer the data package;

相应的，所述单片机具体用于在接收到表征开始标志的数据包之后，接收所述上位机生成的lane配置信息，并在接收到表征结束标志的数据包之后，将所述lane配置信息传输至FPGA。Correspondingly, the single-chip microcomputer is specifically configured to receive the lane configuration information generated by the host computer after receiving the data packet representing the start flag, and transmit the lane configuration information after receiving the data packet representing the end flag. to the FPGA.

优选地，所述组合系统还包括：Preferably, the combined system further includes:

与所述单片机连接的第一指示装置；所述单片机还用于在接收到表征结束标志的数据包之后，控制所述第一指示装置发出表征与上位机握手成功的指示信息，并在将所述lane配置信息传输至FPGA之后，控制所述第一指示装置发出表征与FPGA握手成功的指示信息。A first indicating device connected to the single-chip computer; the single-chip computer is also used to control the first indicating device to send out indicating information indicating that the handshake with the host computer is successful after receiving the data packet representing the end mark, and after receiving the data packet representing the end mark After the lane configuration information is transmitted to the FPGA, the first instructing device is controlled to send out indication information indicating that the handshake with the FPGA is successful.

优选地，所述组合系统还包括：Preferably, the combined system further includes:

与所述FPGA连接的第二指示装置；所述FPGA还用于获取所述非标准PCIe接口和所述标准PCIe接口的lane活跃状态，并控制所述第二指示装置发出表征所述lane活跃状态的指示信息。a second indicating device connected to the FPGA; the FPGA is further configured to acquire the lane active state of the non-standard PCIe interface and the standard PCIe interface, and control the second indicating device to issue a signal representing the lane active state instruction information.

优选地，所述FPGA还用于：Preferably, the FPGA is also used for:

预先设置用于一一保存所述非标准PCIe接口的N条lane各自对应的配置信息的N个控制寄存器；其中，N为正整数；Pre-set N control registers for saving the configuration information corresponding to the N lanes of the non-standard PCIe interface one by one; wherein, N is a positive integer;

在接收到lane配置信息后，将所述非标准PCIe接口的N条lane各自对应的配置信息一一写入对应控制寄存器。After receiving the lane configuration information, write the respective configuration information corresponding to the N lanes of the non-standard PCIe interface into the corresponding control registers one by one.

优选地，所述FPGA还用于预先设置用于保存所述非标准PCIe接口和所述标准PCIe接口的可用状态的控制寄存器，以将两接口的实际可用状态写入对应控制寄存器。Preferably, the FPGA is further configured to preset control registers for saving the available states of the non-standard PCIe interface and the standard PCIe interface, so as to write the actual available states of the two interfaces into the corresponding control registers.

为解决上述技术问题，本发明还提供了一种PCIe设备lane的组合方法，应用于上述任一种PCIe设备lane的组合系统，包括：In order to solve the above-mentioned technical problems, the present invention also provides a method for combining PCIe device lanes, which is applied to any combination system of the above-mentioned PCIe device lanes, including:

上位机根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息；The host computer generates lane configuration information representing the lane combination mode between the two interfaces according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface;

控制装置根据所述lane配置信息，将所述非标准PCIe接口和所述标准PCIe接口的lane进行组合，以实现两接口的通信连接。The control device combines the non-standard PCIe interface and the lane of the standard PCIe interface according to the lane configuration information, so as to realize the communication connection of the two interfaces.

本发明提供了一种PCIe设备物理lane的组合系统，包括上位机和控制装置。上位机根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息至控制装置；控制装置根据lane配置信息，将非标准PCIe接口和标准PCIe接口的lane进行组合，以实现两接口的通信连接。可见，本申请可实现非标准PCIe接口和标准PCIe接口的lane自由组合，从而有利于自定义的PCIe接口连接设备的开发设计。The invention provides a combination system of PCIe equipment physical lanes, including a host computer and a control device. The host computer generates lane configuration information representing the lane combination mode between the two interfaces to the control device according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface; the control device combines the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information. The lanes of the interface are combined to realize the communication connection between the two interfaces. It can be seen that the present application can realize the free combination of lanes of non-standard PCIe interfaces and standard PCIe interfaces, thereby facilitating the development and design of customized PCIe interface connection devices.

本发明还提供了一种PCIe设备物理lane的组合方法，与上述组合系统具有相同的有益效果。The present invention also provides a method for combining physical lanes of PCIe devices, which has the same beneficial effects as the above-mentioned combined system.

附图说明Description of drawings

为了更清楚地说明本发明实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the prior art and the accompanying drawings required in the embodiments. Obviously, the drawings in the following description are only some of the present invention. In the embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

图1为本发明实施例提供的一种PCIe设备物理lane的组合系统的结构示意图；FIG. 1 is a schematic structural diagram of a combined system of a PCIe device physical lane according to an embodiment of the present invention;

图2为本发明实施例提供的一种PCIe设备物理lane的组合系统的具体结构示意图。FIG. 2 is a schematic structural diagram of a combination system of a physical lane of a PCIe device according to an embodiment of the present invention.

具体实施方式Detailed ways

本发明的核心是提供一种PCIe设备物理lane的组合系统及方法，可实现非标准PCIe接口和标准PCIe接口的lane自由组合，从而有利于自定义的PCIe接口连接设备的开发设计。The core of the present invention is to provide a system and method for combining physical lanes of PCIe devices, which can realize the free combination of lanes of non-standard PCIe interfaces and standard PCIe interfaces, thereby facilitating the development and design of customized PCIe interface connection devices.

为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

请参照图1，图1为本发明实施例提供的一种PCIe设备物理lane的组合系统的结构示意图。Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a system for combining physical lanes of PCIe devices according to an embodiment of the present invention.

该PCIe设备物理lane的组合系统包括：The combined system of the PCIe device physical lanes includes:

上位机1，用于根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息；The upper computer 1 is used to generate lane configuration information representing the lane combination mode between the two interfaces according to the lane combination requirement between the non-standard PCIe interface and the standard PCIe interface;

分别与非标准PCIe接口、标准PCIe接口及上位机1连接的控制装置2，用于根据lane配置信息，将非标准PCIe接口和标准PCIe接口的lane进行组合，以实现两接口的通信连接。The control device 2, which is respectively connected with the non-standard PCIe interface, the standard PCIe interface and the upper computer 1, is used for combining the non-standard PCIe interface and the lane of the standard PCIe interface according to the lane configuration information, so as to realize the communication connection of the two interfaces.

具体地，本申请的PCIe设备物理lane的组合系统包括上位机1和控制装置2，其工作原理为：Specifically, the combination system of the PCIe device physical lane of the present application includes a host computer 1 and a control device 2, and its working principle is:

用户可在上位机1上输入非标准PCIe接口和标准PCIe接口之间的lane组合需求，即非标准PCIe接口的哪条lane和标准PCIe接口的哪条lane通信连接。上位机1根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，可生成表征非标准PCIe接口和标准PCIe接口之间lane组合方式的lane配置信息，并将lane配置信息下发至控制装置2。The user can input the lane combination requirement between the non-standard PCIe interface and the standard PCIe interface on the host computer 1, that is, which lane of the non-standard PCIe interface is connected to which lane of the standard PCIe interface is for communication connection. The host computer 1 can generate lane configuration information representing the lane combination mode between the non-standard PCIe interface and the standard PCIe interface according to the lane combination requirement between the non-standard PCIe interface and the standard PCIe interface, and send the lane configuration information to the control device 2.

控制装置2在接收到上位机1下发的lane配置信息之后，可根据lane配置信息将非标准PCIe接口和标准PCIe接口的lane进行组合，即将非标准PCIe接口的各条lane和标准PCIe接口的各条lane一一建立起通信连接，从而实现非标准PCIe接口和标准PCIe接口之间的通信连接。After receiving the lane configuration information sent by the host computer 1, the control device 2 can combine the lanes of the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information, that is, the lanes of the non-standard PCIe interface and the standard PCIe interface. Each lane establishes a communication connection one by one, thereby realizing the communication connection between the non-standard PCIe interface and the standard PCIe interface.

本发明提供了一种PCIe设备物理lane的组合系统，包括上位机和控制装置。上位机根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息至控制装置；控制装置根据lane配置信息，将非标准PCIe接口和标准PCIe接口的lane进行组合，以实现两接口的通信连接。可见，本申请可实现非标准PCIe接口和标准PCIe接口的lane自由组合，从而有利于自定义的PCIe接口连接设备的开发设计。The invention provides a combination system of PCIe equipment physical lanes, including a host computer and a control device. The host computer generates lane configuration information representing the lane combination mode between the two interfaces to the control device according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface; the control device combines the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information. The lanes of the interface are combined to realize the communication connection between the two interfaces. It can be seen that the present application can realize the free combination of lanes of non-standard PCIe interfaces and standard PCIe interfaces, thereby facilitating the development and design of customized PCIe interface connection devices.

在上述实施例的基础上：On the basis of the above-mentioned embodiment:

作为一种可选的实施例，上位机1具体用于：As an optional embodiment, the host computer 1 is specifically used for:

根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，按照非标准PCIe接口的lane顺序，依次生成表征将非标准PCIe接口的第n条lane配置到标准PCIe接口的第m条lane的配置数据包；其中，n、m均为正整数；According to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface, and in accordance with the lane order of the non-standard PCIe interface, the configuration representing the configuration of the nth lane of the non-standard PCIe interface to the mth lane of the standard PCIe interface is sequentially generated Data packet; among them, n and m are positive integers;

则控制装置2具体用于根据依次生成的配置数据包，对应将非标准PCIe接口的第n条lane配置到标准PCIe接口的第m条lane，以完成非标准PCIe接口和标准PCIe接口的lane组合。Then the control device 2 is specifically configured to configure the nth lane of the non-standard PCIe interface to the mth lane of the standard PCIe interface according to the configuration data packets generated in turn, so as to complete the lane combination of the non-standard PCIe interface and the standard PCIe interface. .

具体地，本申请的上位机1根据非标准PCIe接口和标准PCIe接口之间的lane组合需求(设本申请所涉及的PCIe接口的lane条数为N)，生成N个配置数据包，其中，每个配置数据包均表征的是非标准PCIe接口的一条lane和标准PCIe接口的哪条lane通信连接，即非标准PCIe接口的一条lane配置到标准PCIe接口的哪条lane。Specifically, the host computer 1 of the present application generates N configuration data packets according to the lane combination requirement between the non-standard PCIe interface and the standard PCIe interface (assuming that the number of lanes of the PCIe interface involved in the present application is N), wherein, Each configuration data packet represents a communication connection between a lane of the non-standard PCIe interface and the lane of the standard PCIe interface, that is, which lane of the non-standard PCIe interface is configured to which lane of the standard PCIe interface.

更具体地，上位机1按照非标准PCIe接口的lane顺序依次生成N个配置数据包，也就是说，第n个生成的配置数据包表征的是非标准PCIe接口的第n条lane配置到标准PCIe接口的哪条lane。比如，第n个生成的配置数据包中写入的数据为m，表示非标准PCIe接口的第n条lane配置到标准PCIe接口的第m条lane。More specifically, the host computer 1 sequentially generates N configuration data packets according to the lane order of the non-standard PCIe interface, that is to say, the configuration data packet generated by the nth represents that the nth lane of the non-standard PCIe interface is configured to the standard PCIe interface. Which lane of the interface. For example, the data written in the nth generated configuration data packet is m, indicating that the nth lane of the non-standard PCIe interface is configured to the mth lane of the standard PCIe interface.

基于此，控制装置2根据上位机1依次生成的配置数据包，对应将非标准PCIe接口的第n条lane配置到标准PCIe接口的第m条lane，最终完成非标准PCIe接口和标准PCIe接口的所有lane组合。Based on this, the control device 2 configures the n-th lane of the non-standard PCIe interface to the m-th lane of the standard PCIe interface according to the configuration data packets sequentially generated by the host computer 1, and finally completes the configuration of the non-standard PCIe interface and the standard PCIe interface. All lane combinations.

请参照图2，图2为本发明实施例提供的一种PCIe设备物理lane的组合系统的具体结构示意图Please refer to FIG. 2. FIG. 2 is a schematic diagram of a specific structure of a combined system of a PCIe device physical lane provided by an embodiment of the present invention.

作为一种可选的实施例，控制装置2包括：As an optional embodiment, the control device 2 includes:

与上位机1连接的单片机，用于接收上位机1生成的lane配置信息，并将lane配置信息传输至FPGA；The single-chip microcomputer connected to the host computer 1 is used to receive the lane configuration information generated by the host computer 1 and transmit the lane configuration information to the FPGA;

分别与非标准PCIe接口和标准PCIe接口连接的FPGA，用于根据lane配置信息，将非标准PCIe接口和标准PCIe接口的lane进行组合，以实现两接口的通信连接。The FPGA connected to the non-standard PCIe interface and the standard PCIe interface respectively is used to combine the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information, so as to realize the communication connection of the two interfaces.

具体地，本申请的控制装置2结构简单，包括单片机和FPGA(Field ProgrammableGateArray，现场可编程门阵列)，其工作原理为：Specifically, the control device 2 of the present application has a simple structure, including a single-chip microcomputer and an FPGA (Field Programmable Gate Array, Field Programmable Gate Array), and its working principle is:

上位机1将lane配置信息下发至单片机。单片机在接收到上位机1下发的lane配置信息后，将lane配置信息传输至FPGA。FPGA根据lane配置信息将非标准PCIe接口和标准PCIe接口的lane进行组合，从而实现非标准PCIe接口和标准PCIe接口之间的通信连接。The host computer 1 sends the lane configuration information to the microcontroller. After receiving the lane configuration information sent by the host computer 1, the single-chip microcomputer transmits the lane configuration information to the FPGA. The FPGA combines the non-standard PCIe interface and the lane of the standard PCIe interface according to the lane configuration information, so as to realize the communication connection between the non-standard PCIe interface and the standard PCIe interface.

更具体地，如图2所示，Downstream连接器为非标卡的自定义连接器，连接自定义非标准PCIe接口；Upstream连接器为标卡的自定义连接器，连接自定义标准PCIe接口。上位机1和单片机可通过RS-232串口通信方式进行通信，单片机和FPGA可通过I2C总线进行通讯。More specifically, as shown in FIG. 2 , the Downstream connector is a custom connector of a non-standard card, and is connected to a custom non-standard PCIe interface; the Upstream connector is a custom connector of a standard card, and is connected to a custom standard PCIe interface. The host computer 1 and the single-chip computer can communicate through the RS-232 serial port communication mode, and the single-chip computer and the FPGA can communicate through the I 2 C bus.

作为一种可选的实施例，上位机1还用于在发送lane配置信息之前，向单片机发送表征开始标志的数据包，并在发送完lane配置信息之后，向单片机发送表征结束标志的数据包；As an optional embodiment, the host computer 1 is further configured to send a data packet representing the start flag to the microcontroller before sending the lane configuration information, and after sending the lane configuration information, send the data packet representing the end flag to the microcontroller ;

相应的，单片机具体用于在接收到表征开始标志的数据包之后，接收上位机1生成的lane配置信息，并在接收到表征结束标志的数据包之后，将lane配置信息传输至FPGA。Correspondingly, the single-chip microcomputer is specifically configured to receive the lane configuration information generated by the host computer 1 after receiving the data packet representing the start flag, and transmit the lane configuration information to the FPGA after receiving the data packet representing the end flag.

进一步地，本申请还可在发送lane配置信息之前向单片机发送表征开始标志的数据包，在发送完lane配置信息之后向单片机发送表征结束标志的数据包，以由单片机根据表征开始标志和结束标志的数据包确定与lane配置信息对应的配置数据包。Further, the present application can also send the data packet representing the start flag to the single-chip microcomputer before sending the lane configuration information, and send the data packet representing the end flag to the single-chip microcomputer after sending the lane configuration information, so that the single-chip microcomputer can characterize the start flag and the end flag according to the single-chip microcomputer. The data packets determine the configuration data packets corresponding to the lane configuration information.

比如，本申请所涉及的PCIe接口的lane条数为24，则上位机1和单片机整个通信的过程包括26个数据包，第1个数据包为“开始标志”，如由字节“8’b10101010”表示，第26个数据包为“结束标志”，如由字节“8’b01010101”表示，第2～25共24个数据包为与lane配置信息对应的配置数据包。For example, if the number of lanes of the PCIe interface involved in this application is 24, the entire communication process between the host computer 1 and the microcontroller includes 26 data packets, and the first data packet is the "start mark", such as the byte "8' b10101010" indicates that the 26th data packet is the "end flag", as represented by the byte "8'b01010101", and the 24th data packets from the 2nd to the 25th are the configuration data packets corresponding to the lane configuration information.

作为一种可选的实施例，组合系统还包括：As an optional embodiment, the combined system further includes:

与单片机连接的第一指示装置；单片机还用于在接收到表征结束标志的数据包之后，控制第一指示装置发出表征与上位机1握手成功的指示信息，并在将lane配置信息传输至FPGA之后，控制第一指示装置发出表征与FPGA握手成功的指示信息。The first indicating device connected with the single-chip microcomputer; the single-chip microcomputer is also used to control the first indicating device to send out the indicating information indicating the successful handshake with the upper computer 1 after receiving the data packet representing the end mark, and transmit the lane configuration information to the FPGA Afterwards, the first instructing device is controlled to send out indication information indicating that the handshake with the FPGA is successful.

进一步地，本申请的组合系统还包括第一指示装置，其工作原理为：Further, the combined system of the present application also includes a first indicating device, and its working principle is:

单片机在接收到表征结束标志的数据包之后，控制第一指示装置发出表征与上位机1握手成功的指示信息，供用户查看，以使用户了解到单片机成功接收到上位机1下发的lane配置信息。单片机在将lane配置信息传输至FPGA之后，控制第一指示装置发出表征与FPGA握手成功的指示信息，供用户查看，以使用户了解到单片机成功将lane配置信息传输至FPGA。After the single-chip microcomputer receives the data packet representing the end flag, it controls the first indicating device to send out the indication information indicating the successful handshake with the host computer 1 for the user to check, so that the user can know that the single-chip microcomputer has successfully received the lane configuration issued by the host computer 1. information. After the single-chip microcomputer transmits the lane configuration information to the FPGA, it controls the first indicating device to send out indication information indicating a successful handshake with the FPGA for the user to view, so that the user can know that the single-chip microcomputer successfully transmits the lane configuration information to the FPGA.

作为一种可选的实施例，组合系统还包括：As an optional embodiment, the combined system further includes:

与FPGA连接的第二指示装置；FPGA还用于获取非标准PCIe接口和标准PCIe接口的lane活跃状态，并控制第二指示装置发出表征lane活跃状态的指示信息。a second indicating device connected to the FPGA; the FPGA is further configured to acquire the lane active state of the non-standard PCIe interface and the standard PCIe interface, and control the second indicating device to send out indicating information representing the lane active state.

进一步地，本申请的组合系统还包括第二指示装置，其工作原理为：Further, the combined system of the present application also includes a second indicating device, and its working principle is:

FPGA可获取非标准PCIe接口和标准PCIe接口的lane活跃状态(活跃/active or不活跃/inactive)，并控制第二指示装置发出表征lane活跃状态的指示信息，供用户查看，以使用户了解到非标准PCIe接口和标准PCIe接口的哪些lane活跃、哪些lane不活跃。The FPGA can obtain the lane active state (active/active or inactive/inactive) of the non-standard PCIe interface and the standard PCIe interface, and control the second indicating device to send out indication information representing the active state of the lane for the user to view, so that the user can understand Which lanes of the non-standard PCIe interface and the standard PCIe interface are active and which are inactive.

更具体地，如图2所示，本申请的第一指示装置和第二指示装置均可由指示灯实现。More specifically, as shown in FIG. 2 , both the first indicating device and the second indicating device of the present application can be implemented by an indicator light.

作为一种可选的实施例，FPGA还用于：As an optional embodiment, the FPGA is also used for:

预先设置用于一一保存非标准PCIe接口的N条lane各自对应的配置信息的N个控制寄存器；其中，N为正整数；Pre-set N control registers for saving the configuration information corresponding to the N lanes of the non-standard PCIe interface one by one; wherein, N is a positive integer;

在接收到lane配置信息后，将非标准PCIe接口的N条lane各自对应的配置信息一一写入对应控制寄存器。After receiving the lane configuration information, write the configuration information corresponding to each of the N lanes of the non-standard PCIe interface into the corresponding control registers one by one.

进一步地，本申请的FPGA还可提前设置N个控制寄存器，每个控制寄存器均用于保存非标准PCIe接口的一条lane对应的配置信息。则FPGA在接收到lane配置信息后，将非标准PCIe接口的N条lane各自对应的配置信息一一写入对应控制寄存器，便于后续读取lane配置信息。Further, the FPGA of the present application may further set N control registers in advance, and each control register is used to store configuration information corresponding to a lane of a non-standard PCIe interface. Then, after receiving the lane configuration information, the FPGA writes the configuration information corresponding to the N lanes of the non-standard PCIe interface into the corresponding control registers one by one, so as to facilitate subsequent reading of the lane configuration information.

作为一种可选的实施例，FPGA还用于预先设置用于保存非标准PCIe接口和标准PCIe接口的可用状态的控制寄存器，以将两接口的实际可用状态写入对应控制寄存器。As an optional embodiment, the FPGA is further configured to preset control registers for saving the available states of the non-standard PCIe interface and the standard PCIe interface, so as to write the actual available states of the two interfaces into the corresponding control registers.

进一步地，本申请的FPGA还可提前设置一个用于保存非标准PCIe接口和标准PCIe接口的可用状态(enable/可用状态：可进行数据通信；disable/禁用状态：无法进行数据通信)的控制寄存器。则FPGA在获取非标准PCIe接口和标准PCIe接口的实际可用状态后，将两接口的实际可用状态写入此控制寄存器，供用户后续读取查看。Further, the FPGA of the present application can also set in advance a control register for saving the available states of the non-standard PCIe interface and the standard PCIe interface (enable/available state: data communication is possible; disable/disabled state: data communication cannot be performed). . Then, after obtaining the actual available status of the non-standard PCIe interface and the standard PCIe interface, the FPGA writes the actual available status of the two interfaces into this control register for the user to read and check later.

比如，本申请所涉及的PCIe接口的lane条数为24，则需在FPGA内部定义25个控制寄存器地址，控制寄存器地址LAN_CTL_ADDR从0x00到0x18，后续直接定义为LAN_CTL_ADDR[24:0]。其中，第一个控制寄存器用于保存非标准PCIe接口和标准PCIe接口的可用状态，第n个控制寄存器用于保存非标准PCIe接口的第n-1条lane对应的配置信息，每个控制寄存器地址对应有3个8bit的DATA(数据)，后续直接定义为DATA[23:0]。For example, if the number of lanes of the PCIe interface involved in this application is 24, 25 control register addresses need to be defined inside the FPGA. The control register address LAN_CTL_ADDR is from 0x00 to 0x18, and is directly defined as LAN_CTL_ADDR[24:0]. Among them, the first control register is used to save the available state of the non-standard PCIe interface and the standard PCIe interface, the nth control register is used to save the configuration information corresponding to the n-1th lane of the non-standard PCIe interface, each control register The address corresponds to three 8-bit DATA (data), which are directly defined as DATA[23:0].

LAN_CTL_ADDR[0]对应的DATA[23:0]＝0x0时，接口处于disable状态；对应的DATA[23:0]＝0x1时，接口处于enable状态。When DATA[23:0] corresponding to LAN_CTL_ADDR[0]=0x0, the interface is in the disabled state; when the corresponding DATA[23:0]=0x1, the interface is in the enabled state.

LAN_CTL_ADDR[24：1]分别控制24条lane的分配情况，如：LAN_CTL_ADDR[24:1] respectively controls the allocation of 24 lanes, such as:

1)LAN_CTL_ADDR[1]—DATA[23:0]＝24’b0000000000000000000000011)LAN_CTL_ADDR[1]—DATA[23:0]=24’b000000000000000000000001

LAN_CTL_ADDR[2]—DATA[23:0]＝24’b000000000000000000000010LAN_CTL_ADDR[2]—DATA[23:0]=24’b000000000000000000000010

LAN_CTL_ADDR[3]—DATA[23:0]＝24’b000000000000000000000100LAN_CTL_ADDR[3]—DATA[23:0]=24’b000000000000000000000100

LAN_CTL_ADDR[4]—DATA[23:0]＝24’b000000000000000000001000LAN_CTL_ADDR[4]—DATA[23:0]=24’b000000000000000000001000

其余LAN_CTL_ADDR[24：5]对应的DATA[23:0]＝24’b0的话，则将Downstream连接器的1～4条lane按顺序分配给Upstream连接器的1～4条lane。If the DATA[23:0] corresponding to the remaining LAN_CTL_ADDR[24:5] = 24'b0, then assign 1 to 4 lanes of the Downstream connector to 1 to 4 lanes of the Upstream connector in sequence.

2)LAN_CTL_ADDR[1]—DATA[23:0]＝24’b0000000000000000000010002)LAN_CTL_ADDR[1]—DATA[23:0]=24’b000000000000000000001000

LAN_CTL_ADDR[2]—DATA[23:0]＝24’b000000000000000000000100LAN_CTL_ADDR[2]—DATA[23:0]=24’b000000000000000000000100

LAN_CTL_ADDR[3]—DATA[23:0]＝24’b000000000000000000000010LAN_CTL_ADDR[3]—DATA[23:0]=24’b000000000000000000000010

LAN_CTL_ADDR[4]—DATA[23:0]＝24’b000000000000000000000001LAN_CTL_ADDR[4]—DATA[23:0]=24’b000000000000000000000001

其余LAN_CTL_ADDR[24：5]对应的DATA[23:0]＝24’b0的话，则将Downstream连接器的1～4条lane按反序分配给Upstream连接器的1～4条lane。If the DATA[23:0] corresponding to the other LAN_CTL_ADDR[24:5] = 24'b0, then assign 1 to 4 lanes of the Downstream connector to 1 to 4 lanes of the Upstream connector in reverse order.

3)LAN_CTL_ADDR[24]—DATA[23:0]＝24’b0000000000000000000000013) LAN_CTL_ADDR[24]—DATA[23:0]=24’b000000000000000000000001

LAN_CTL_ADDR[23]—DATA[23:0]＝24’b000000000000000000000010LAN_CTL_ADDR[23]—DATA[23:0]=24’b000000000000000000000010

LAN_CTL_ADDR[22]—DATA[23:0]＝24’b000000000000000000000100LAN_CTL_ADDR[22]—DATA[23:0]=24’b000000000000000000000100

LAN_CTL_ADDR[21]—DATA[23:0]＝24’b000000000000000000001000LAN_CTL_ADDR[21]—DATA[23:0]=24’b000000000000000000001000

其余LAN_CTL_ADDR[20：1]对应的DATA[23:0]＝24’b0的话，则将Downstream连接器的高4lane(21～24lane)按反序分配给Upstream连接器的1～4条lane。If the DATA[23:0] corresponding to the remaining LAN_CTL_ADDR[20:1]=24'b0, then assign the high 4 lanes (21-24lane) of the Downstream connector to 1-4 lanes of the Upstream connector in reverse order.

本申请还提供了一种PCIe设备lane的组合方法，应用于上述任一种PCIe设备lane的组合系统，包括：The present application also provides a method for combining PCIe device lanes, which is applied to any of the above-mentioned combined systems for PCIe device lanes, including:

上位机根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息；The host computer generates lane configuration information representing the lane combination mode between the two interfaces according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface;

控制装置根据lane配置信息，将非标准PCIe接口和标准PCIe接口的lane进行组合，以实现两接口的通信连接。The control device combines the non-standard PCIe interface and the lane of the standard PCIe interface according to the lane configuration information, so as to realize the communication connection of the two interfaces.

本申请提供的组合方法的介绍请参考上述组合系统的实施例，本申请在此不再赘述。For the introduction of the combination method provided by this application, please refer to the above-mentioned embodiment of the combination system, which will not be repeated in this application.

还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should also be noted that, in this specification, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations. There is no such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其他实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1.一种PCIe设备物理lane的组合系统，其特征在于，包括：1. a combination system of PCIe device physical lane, is characterized in that, comprises: 上位机，用于根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息；The upper computer is used to generate lane configuration information representing the lane combination mode between the two interfaces according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface; 分别与所述非标准PCIe接口、所述标准PCIe接口及所述上位机连接的控制装置，用于根据所述lane配置信息，将所述非标准PCIe接口和所述标准PCIe接口的lane进行组合，以实现两接口的通信连接。A control device connected to the non-standard PCIe interface, the standard PCIe interface and the host computer respectively, for combining the lanes of the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information , in order to realize the communication connection between the two interfaces. 2.如权利要求1所述的PCIe设备lane的组合系统，其特征在于，所述上位机具体用于：2. the combination system of PCIe equipment lane as claimed in claim 1, is characterized in that, described host computer is specifically used for: 根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，按照所述非标准PCIe接口的lane顺序，依次生成表征将所述非标准PCIe接口的第n条lane配置到所述标准PCIe接口的第m条lane的配置数据包；其中，n、m均为正整数；According to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface, and in accordance with the lane order of the non-standard PCIe interface, sequentially generate a lane representing the configuration of the nth lane of the non-standard PCIe interface to the standard PCIe interface. The configuration data packet of the mth lane; among them, n and m are both positive integers; 则所述控制装置具体用于根据依次生成的配置数据包，对应将所述非标准PCIe接口的第n条lane配置到所述标准PCIe接口的第m条lane，以完成所述非标准PCIe接口和所述标准PCIe接口的lane组合。Then the control device is specifically configured to configure the nth lane of the non-standard PCIe interface to the mth lane of the standard PCIe interface according to the sequentially generated configuration data packets, so as to complete the non-standard PCIe interface. and the lane combination of the standard PCIe interface. 3.如权利要求2所述的PCIe设备lane的组合系统，其特征在于，所述控制装置包括：3. The combination system of PCIe device lane as claimed in claim 2, wherein the control device comprises: 与所述上位机连接的单片机，用于接收所述上位机生成的lane配置信息，并将所述lane配置信息传输至FPGA；The single-chip microcomputer connected with the host computer is used to receive the lane configuration information generated by the host computer, and transmit the lane configuration information to the FPGA; 分别与所述非标准PCIe接口和所述标准PCIe接口连接的FPGA，用于根据所述lane配置信息，将所述非标准PCIe接口和所述标准PCIe接口的lane进行组合，以实现两接口的通信连接。The FPGAs respectively connected with the non-standard PCIe interface and the standard PCIe interface are used to combine the lanes of the non-standard PCIe interface and the standard PCIe interface according to the lane configuration information, so as to realize the two interfaces. communication connection. 4.如权利要求3所述的PCIe设备lane的组合系统，其特征在于，所述上位机还用于在发送所述lane配置信息之前，向所述单片机发送表征开始标志的数据包，并在发送完所述lane配置信息之后，向所述单片机发送表征结束标志的数据包；4. the combination system of PCIe equipment lane as claimed in claim 3, it is characterized in that, described host computer is also used for, before sending described lane configuration information, to described single-chip computer, send the data packet that characterizes start mark, and in After sending the lane configuration information, send a data packet representing an end mark to the single-chip microcomputer; 相应的，所述单片机具体用于在接收到表征开始标志的数据包之后，接收所述上位机生成的lane配置信息，并在接收到表征结束标志的数据包之后，将所述lane配置信息传输至FPGA。Correspondingly, the single-chip microcomputer is specifically configured to receive the lane configuration information generated by the host computer after receiving the data packet representing the start flag, and after receiving the data packet representing the end flag, transmit the lane configuration information. to the FPGA. 5.如权利要求4所述的PCIe设备lane的组合系统，其特征在于，所述组合系统还包括：5. The combination system of PCIe device lanes according to claim 4, wherein the combination system further comprises: 与所述单片机连接的第一指示装置；所述单片机还用于在接收到表征结束标志的数据包之后，控制所述第一指示装置发出表征与上位机握手成功的指示信息，并在将所述lane配置信息传输至FPGA之后，控制所述第一指示装置发出表征与FPGA握手成功的指示信息。A first indicating device connected to the single-chip microcomputer; the single-chip computer is also used to control the first indicating device to send out indicating information indicating that the handshake with the host computer is successful after receiving the data packet representing the end mark, and after receiving the data packet representing the end mark After the lane configuration information is transmitted to the FPGA, the first instructing device is controlled to send out indication information indicating that the handshake with the FPGA is successful. 6.如权利要求3所述的PCIe设备lane的组合系统，其特征在于，所述组合系统还包括：6. The combination system of PCIe device lanes according to claim 3, wherein the combination system further comprises: 与所述FPGA连接的第二指示装置；所述FPGA还用于获取所述非标准PCIe接口和所述标准PCIe接口的lane活跃状态，并控制所述第二指示装置发出表征所述lane活跃状态的指示信息。a second indicating device connected to the FPGA; the FPGA is further configured to acquire the lane active state of the non-standard PCIe interface and the standard PCIe interface, and control the second indicating device to issue a signal representing the lane active state instruction information. 7.如权利要求3-6任一项所述的PCIe设备lane的组合系统，其特征在于，所述FPGA还用于：7. the combination system of PCIe equipment lane as described in any one of claim 3-6, is characterized in that, described FPGA is also used for: 预先设置用于一一保存所述非标准PCIe接口的N条lane各自对应的配置信息的N个控制寄存器；其中，N为正整数；Pre-set N control registers for saving the configuration information corresponding to the N lanes of the non-standard PCIe interface one by one; wherein, N is a positive integer; 在接收到lane配置信息后，将所述非标准PCIe接口的N条lane各自对应的配置信息一一写入对应控制寄存器。After receiving the lane configuration information, write the respective configuration information corresponding to the N lanes of the non-standard PCIe interface into the corresponding control registers one by one. 8.如权利要求7所述的PCIe设备lane的组合系统，其特征在于，所述FPGA还用于预先设置用于保存所述非标准PCIe接口和所述标准PCIe接口的可用状态的控制寄存器，以将两接口的实际可用状态写入对应控制寄存器。8. the combination system of PCIe equipment lane as claimed in claim 7, is characterized in that, described FPGA is also used for presetting the control register that is used to save the available state of described non-standard PCIe interface and described standard PCIe interface, In order to write the actual available state of the two interfaces into the corresponding control register. 9.一种PCIe设备lane的组合方法，其特征在于，应用于如权利要求1-8任一项所述的PCIe设备lane的组合系统，包括：9. a combination method of PCIe device lane, is characterized in that, is applied to the combination system of PCIe device lane as described in any one of claim 1-8, comprising: 上位机根据非标准PCIe接口和标准PCIe接口之间的lane组合需求，生成表征两接口之间lane组合方式的lane配置信息；The host computer generates lane configuration information representing the lane combination mode between the two interfaces according to the lane combination requirements between the non-standard PCIe interface and the standard PCIe interface; 控制装置根据所述lane配置信息，将所述非标准PCIe接口和所述标准PCIe接口的lane进行组合，以实现两接口的通信连接。The control device combines the non-standard PCIe interface and the lane of the standard PCIe interface according to the lane configuration information, so as to realize the communication connection of the two interfaces.
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