JPH0644776B2 - Line control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Two sets of line control units are provided in order to cope with demands for line type, line throughput improvement, duplex configuration, etc. A communication means and a shared memory are provided between the control units, and one side is used as a main side (master) to simplify control on the main device side.

[Industrial application field]

 The present invention relates to improvement of a line control device.

Data communication has become widespread with the development of various protocols and the improvement of communication speed, but as a result, there are various line types and the problem of connection between devices having different line types has arisen.

On the other hand, as the importance of data communication has increased, measures against line system failures have been demanded.

However, it is difficult in terms of hardware and software to prepare a line control device for each system,
There is a demand for a line control device that can easily meet these demands.

[Conventional technology]

FIG. 3 (a) is a block diagram of a conventional line control device, and FIG. 3 (b).
FIG. 4 is an explanatory diagram of a duplication method.

In FIG. 3 (a), the line control device 3 uses the common bus 10
An interface (IF) controller 4 connected to 0 for transferring control data to and from the main processor (main CPU) 1 while transferring control information, a line control program for controlling various protocols, a memory 6 for storing transfer data, etc. It is composed of a processor CPU 5, a line interface control unit 7 and the like, and a transmission unit and a reception unit are formed by the line control program. That is, the transmission process ... By activating the main CPU 1, the transmission data existing in the main memory 2 is taken into the memory 6, processed into a predetermined protocol format, and then sent to the external line 53 via the line interface control unit 7. To do.

Reception process: Received data received from the line is disassembled and analyzed, then transferred to the main memory 2 and notified to the main CPU 1.

Here, depending on the content of the received data, it may be discarded in the line control device 3 and the transmission unit may be requested to transmit the response information.

The line interface control unit 7 includes a register which the CPU 5 reads / writes, and has a function of performing parallel-serial conversion and serial-parallel conversion of transmission / reception data to perform full-duplex communication, a function of selecting a line speed, and the like. It is equipped with.

In the line control device, various line types are supported by various protocol controls by the CPU 5, high-speed transfer by DMA (direct memory access) with the main unit, line speed selection, etc. For example, if the line speed is different for the upper and lower lines, or if it is necessary to support full-duplex communication such as LAN (local area network) baseband system, or to duplicate the line control device, two sets of lines A control device is provided, and each main CP
Often U1 is configured to control.

FIG. 3 (b) is a diagram showing an example of a duplex system of the line control device, in which two sets of the same line control device 3 are connected to the common bus 10
0, one of them is set to a standby state, and when a failure is detected on the main side, the main CPU 1 switches the switching unit 8
This is a method of switching the switch to the standby side.

[Problems to be solved by the invention]

When dealing with line types, duplicated configurations, etc., the conventional method of incorporating the same line control device into two sets of devices requires that the main CPU 1 be aware of each line control device and perform transmission / reception control, and in terms of hardware. There is a problem that it is complicated and expensive in terms of software.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a simple line control device capable of coping with a diversified line type and a duplex configuration.

[Means for solving problems]

For the above purpose, the line control device of the present invention includes a main interface control unit (13) for transferring transmission / reception data (51) to / from a main device, as shown in FIG. Line control program (5
An individual memory (16) for storing 0), a processor (17) for performing line control based on the line program (50), and a line interface control section (7) having interface means with an external line (53) And a shared memory (18) for storing the transmission / reception data (51), respectively, in addition to the first and second line control units (10, 11) each of which is provided with the first and second line control units (10, 11). ), A communication means (26) for communicating between the first and second line control units (10, 11), and a line control program (50) including line control means corresponding to each line type as a main device. Load means (27) for further loading, control means (28) for exchanging transmission / reception control information (52) with the main unit via the first line control section (10), and an external line corresponding to the line control means. (53) to the first and second line control units (10, 11) is provided with a switching section (12) for switching connection.

[Action]

Corresponding to various line types such as high-speed lines, lines with different uplink / downlink line speeds, full-band baseband communication, and duplex configuration, two sets of first and second line control units 1 are provided.
0, 11 (10 is the master and 11 is the slave below)
To share the line control with the external line 53
To switch.

Therefore, the corresponding line control program 50 is loaded from each main unit, and the switching unit 12 is switched by the program.

Transmission / reception data 51 to / from the main unit is transferred at high speed by DMA by each main interface control unit 13, and exchange of transmission / reception control information between the main unit and the line control unit is performed by the main interface control on the master side. Through the department. For this reason, the communication means 26 is provided for communicating between the main unit and the slave side via the master side.

The shared memory 18 stores transmission / reception data and is commonly accessed in the duplex configuration.

With the above, line type and duplex are supported,
The main device can perform transmission / reception control without being aware of the two sets of line control units.

An example of correspondence to the line type is shown below.

(1) Corresponding to a line of another system or a line of another device [Fig. 2 (a)-(I) Independent two-line system] Load and switch the line control program 50 having independent transmission / reception control means for master and slave Connection control of each unit 12 to the corresponding external line 53 is performed. With this method, a two-channel line for full-duplex communication can be obtained.

(2) Correspondence to high-speed line [Fig. 2 (a)-(II) Transmission / reception sharing method] The master and the slave are respectively responsible for transmission control and reception control, and are connected to one set of external lines 53.

(3) Corresponding to lines with different upper and lower line speeds [Figure 2 (a)-(II) Transmission and reception sharing method] The transmission and reception are shared in the same manner as (2), and the line speeds are changed respectively.

(4) Correspondence to duplex of line control unit [Fig. 2 (a)-(III) Duplex system of line control unit] Have the same transmission / reception control program 50, connect slave side to standby state, and connect to master side When a failure occurs, control is switched to the slave side.

(5) Line duplication [Fig. 2 (a)-(V) Line duplication method] Two sets of lines are provided between the devices and only one line control unit is operated.

When a failure occurs in the active external line 53, the switching unit 12
To switch to the other external line.

(5) Correspondence to full-duplex communication in half-duplex baseband system [Fig. 2 (a)-(IV) Full-duplex system in baseband] The line is duplexed and the transmission and reception are shared.

When a line control unit or line fails, half-duplex communication is performed in the other system.

As described above, two sets of line control means are provided to correspond to the line types, and since there is only one set of control interface means with the main device, the main device does not need to be aware of the two sets of line control units for transmission / reception. You can control.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 2 (a) is a diagram showing a correspondence example, FIG. 2 (b) is a block diagram of the line control device of the embodiment, FIG. 2 (c) is an operation explanatory diagram of the transmission / reception sharing system, and FIG. 2 (d). Is an operation flowchart of the transmission / reception sharing system, and FIG. 2 (e) is a diagram showing an example of connection with a modem.

〔Constitution〕

Hereinafter, the same object belonging to each of the master line control unit 10 (first line control unit 10) and the slave line control unit 11 (second line control unit 11) will be denoted by the same reference numeral with subscripts a and b.

Reference numerals 13a and 13b denote main interface control units, which have a function of DMA-transmitting the transmission / reception data 51 between the main memory 2 [FIG. 3 (a)] and the shared memory 18, and the main CPU 1 and the master CPU 16a or the slave CPU 16b. Having a function of exchanging transmission / reception control information 52 between them, 14a and 14b are read-only memory ROMs storing an IPL program 54 for loading the line control program 50 from the main memory 2, and 15 is a master CPU 16a. Interface (I / F) registers for communication with the slave CPU 16b, which are composed of a plurality of command and status registers, 16a and 16b are a master CPU and a slave CPU, each of which is a microprocessor or the like. , 17a, 17b, the line control program 50, etc. A shared memory for temporarily storing the transmission / reception data 51, which can be commonly accessed by the master CPU 16a and the slave CPU 16b, 7a and 7b are line interface control units, and the above-mentioned line interface control unit 7 is the same as 7, 12 is a switching unit, the multiplexer MPX20,2
1, 22 and 23 are connected as shown and switched by a transmission switching signal S and a reception switching signal R set in a register (not shown), 24a and b are line drivers DV, and 25a and b are line receivers RV ,.

The communication means 26 is stored in the I / F register 15, and the loading means 27 is stored in the ROMs 14a and 14b.
In the PL program 54, the control means 28 is the main CP described later.
It corresponds to the communication program between U1 and the master CPU 16a.

The line control device having the above-mentioned configuration is composed of, for example, a board,
It is standardized so that it can be attached to various devices.

[Line control program loading]

The operation will be described below by taking the transmission / reception sharing system [FIG. 2 (a)-(II)] as an example. 2 (c) and 2 (d) The line control program 50 is composed of a program for executing line processing such as protocol control. The IPL program 54 stored in the ROMs 14a and 14b allows the main interface control units 13a and 13b to be accessed from the main memory 2. To the individual memories 17a and 17b via

Line control program 50 loaded by the IPL
The configuration of is shown below.

Master line control unit 10-Transmission control program-Communication program with main unit side-Communication program with slave side-Data transfer program with main memory-Switching unit control program Slave line control unit 11-Reception control program-Master side Communication program ・ Data transfer program with main memory.

〔Start-up〕

When the loading is completed, the execution is switched from the IPL program 54 to the loaded line control program 50 based on the instruction of the main CPU 1.

[Line interface settings]

When each line control program 50 is activated, first, the operation mode of the line interface control units 7a and 7b is set, and the line (transmission and reception) switching signals R and S are output by the master line control unit 10 and the predetermined operation is performed. Connected to the line.

With the above processing, the line control device is put into the ready state, and the transmission / reception operation becomes possible.

[Sending operation]

(1) The main CPU 1 outputs a transmission command together with the storage destination of the transmission data through the main interface control unit 13a (Fig. 2 (c), (d) -S1), and based on this, the master CP
The U 16a instructs the main interface control unit 13a to transfer the transmission data from the main memory 2 to the shared memory 18. (S2) (2) The master CPU 16a reads the transmission data from the shared memory 18, generates it in a predetermined protocol format, and requests the line interface control section 7a to transmit it. (S3) (3) The line interface control unit 7a outputs at the set line speed with the addition of start bits, stop bits, parity, etc. (in the case of start-stop type).

(4) This transmission data is output to the external line through the MPX 22 and DV 24a.

(5) The completion of transmission is notified to the main CPU 1 every time frame transmission is completed. (S4) [Reception Operation] (1) The main CPU 1 notifies the master line control unit 10 of buffer information (address and length) in the main memory 2 for storing reception data in advance, and the master line control unit 1
0 receives this and notifies the slave circuit control unit 11 of it. (R1) (2) The received data is received by the line interface control unit 7b through the RV 25a and MPX 21, and the slave C
The PU 16b is notified. (R2) (3) The slave CPU 16 (b) sequentially reads this from the line interface controller 7b and stores it in the shared memory 18,
After analysis and processing, main interface control unit 1
An area on the main memory 2 designated in advance in 3b is designated and transferred. (R3) (4) Each time a frame is received, the master side is notified of the completion of reception via the I / F register 15, and the master line control unit 10 notifies the main CPU 1 of this. (R4) (5) If the received data requires a predetermined response, it is not transferred to the main memory 2 and the master line controller 1
Request 0 to send a response message.

[Redundant system of line control device]

The same transmission / reception control program is loaded on the master and slave sides, the lines are connected so that the slave side is in a standby state, and the master side performs transmission / reception control.

When a predetermined switching state such as a line error occurs on the master side, control is switched to the slave side according to the judgment of the main CPU 1.

When the communication system with the main unit is switched to the slave side, the slave side or the main CPU 1 is provided with the switching means of the switching unit 12.

[Connection with external line]

When the line control device is connected to a modem or a line terminating device (DSU), the switching unit 12 also switches the control line at the same time.

Connection mode to the modem in the transmission / reception sharing system (RS232
The C interface is shown in Fig. 2 (e).

As described above, since two sets of line control units are provided to load the line control programs corresponding to the line types and one set of interface is provided as a communication means with the main unit side, The line type can be supported and the control on the main device side can be simplified.

〔The invention's effect〕

According to the present invention, two sets of line control units are provided to correspond to the line types and the control on the side of the main device is simplified. Therefore, the effect in communication between devices is extremely great.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 (a) is a diagram showing a corresponding example, FIG. 2 (b) is a block diagram of the line control device of the embodiment, and FIG. 2 (c) is a transmission / reception sharing system. 2 (d) is an operation flowchart of the transmission / reception sharing system, FIG. 2 (e) is a diagram showing an example of connection with a modem, and FIG. 3 (a) is a block diagram of a conventional line control device. FIG. 3 (b) is a diagram for explaining the conventional duplexing method. In the figure, 1 is a main processor CPU, 2 is a main memory, 3 is a line control device, 4 is an interface control unit (IF control unit), 5 is a processor CPU, 6 is a memory, and 7, 7a and 7b are line interface control units. , 8 is a switching unit, 10 is a first line control unit (master line control unit), 11 is a second line control unit (slave line control unit), 12 is a switching unit, 13, 13a, 13b are main interface controls Section, 14a and 14b are read-only memory ROMs, 15 is an interface (I / F) register, 16 is a processor, 16a is a master processor CPU, 16b is a slave processor CPU, 17, 17a and 17b are individual memories, 18 is a shared memory 20, 21, 22, 23 are multiplexers MPX, 24a, 24b are line drivers DV, 25a, 25 Is a line receiver RV, 26 is a communication unit, 27 is a load unit, 28 is a control unit, 50 is a line control program, 51 is transmission / reception data, 52 is transmission / reception control information, 53 is an external line, 54 is an IPL program, and 100 is common The bus is.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyuki Mitsuishi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP 59-180741 (JP, A) JP 59-178543 (JP, A)

Claims (1)

[Claims] 1. A main interface control unit (13) for transferring transmission / reception data (51) to and from a main unit, an individual memory (17) for storing a line control program (50), and the line program (50). First and second line control units (10, 11) each having a processor (16) for performing line control based on the above, and a line interface control unit (7) provided with interface means with the external line (53). A line controller configured to include a shared memory (18) for storing transmission / reception data (51) by the first and second line controllers (10, 11), and a first and second line controller. A communication means (26) for communicating with (10,11), a load means (27) for loading a line control program (50) having line control means corresponding to each line type from the main unit, and First and second line control units (10,11) A control means (28) for exchanging transmission / reception control information (52) with the main device via one of the main interface control sections (13) and an external line (53) corresponding to the line control means A line control device comprising: a switching unit (12) for switching connection to each of the first and second line control units (10, 11);