JPH10164128A - Communication processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a communication processor capable of shortening an initialization setting time at the time of starting a system and a change-over time at the time of changing-over the system of a switch part, with respect to the setting of control information and connection information in the communication processor. SOLUTION: This communication processor is provided with the switch part 20 with duplex configuration having a cross connect part 20A and a line terminating control part 20B and a processor with duplex configuration. In this case, a writing memory interfaces for executing the batch transfer of whole control information and connection information of protocol processing parts 30 and line terminating parts 40 are provided in the processor 51A and a difference detecting part 60 for detecting difference between control information and connection information which are transmitted a preceding time and this time is provided in the switch part 20. Then, the batch transfer of control information and connection information is executed from the processor 51A to the switch part 20 by the writing memory interfaces, whole information is processed at the time of initialization setting and, from the succeeding time, only difference between preceding time connection information and control information and this time information is processed in configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to setting of control information and connection information of a communication processing device. A frame relay communication system is an X.264 communication system used in a packet switching system used in data communication. Based on the 25 protocol, the data transmission procedure is greatly simplified, thereby enabling high-speed data transmission.

When starting up a communication processing device used in this frame relay communication system, a cross-connect function is used to arbitrarily connect a line termination unit and a protocol processing unit. It is necessary to set a large amount of control information and connection information for the switch unit.

[0003] Therefore, there is a demand for a communication processing device capable of setting such control information and connection information efficiently.

[0004]

2. Description of the Related Art FIG. 8 is a block diagram for explaining a conventional communication processing apparatus. In the figure, reference numerals 10 and 11 denote 0-system and 1-system processors, 10A and 10B denote 0-system and 1-system switch unit control memories, 20 and 21 denote 0-system and 1-system switch units,
20A is a cross-connect unit, 20B is a line termination control unit,
20C is a control unit, 30 is a protocol processing unit, and 40 is a line termination unit.

[0005] When the system is started up, the communication processing apparatus operates as follows.
A large amount of control information needs to be set for the switch units 20 and 21 (hereinafter, the active system switch unit is referred to as 20 and the standby system switch unit is referred to as 21).

During operation of the communication processing apparatus, an abnormality is detected in the switch unit 20 of the active system (hereinafter referred to as ACT system), and the switch unit 21 of the standby system (hereinafter referred to as SBY system) is detected.
Is switched to the ACT system, a large amount of control information is set in the switch unit 21 from the processor 10, and then the switch unit 21 starts operation as a new ACT system.

[0007]

In the above-mentioned conventional example, an interface for transferring control information and connection information from the processors 10 and 11 to the switch units 20 and 21 has an area in which a large amount of control information can be set at one time. I do not have.
Therefore, the command is edited a plurality of times on the processor 10, 11 side, and the processor 10, 11 and the switch unit 20, 2
It is necessary to transfer the control information and connection information a plurality of times to and from the communication processing device 1, and it takes a long time to start up the communication processing device.

Further, when an abnormality is detected in the ACT switch unit 20 during operation of the communication processing apparatus and the SBY switch unit 21 is switched to the ACT system (here, the switch unit 20 is switched to the ACT system, 21 is a standby system, the operation is the same in the reverse case.) However, it is necessary to set a large amount of control information and connection information from the ACT processor 10 in the switch unit 21. In this case as well, as described in the initial setting at the time of startup, the command writing interface does not have an area in which a large amount of control information and connection information can be set at one time. Editing commands, processor 1
A plurality of transfer control procedures between 0 and the switch unit 21 are required, and it takes a long time to reset a system that can operate normally.

When the ACT processor 10 is executing another process at the time of the system switching of the switch unit, the process waits for the completion of the process and then sets the various information described above. Is performed, the time required for system switching is further increased, and frames transmitted from the line during this switching time are lost.

[0010] Further, the processors 10, 1 having a duplicated configuration.
1 is switched, the switch unit 20 switches to the old ACT.
The control information sent from the system processor 10 cannot be discarded, and an error may occur in the command interface of the new ACT system processor 11 (for example, the old A
If the processor is switched before the command is sent from the CT processor 10 and the status corresponding to the command is not returned, the status is returned to the new ACT processor 11 that has not issued the command. In order to prevent such an error from occurring, it is necessary to delay the initial setting of the new ACT processor 11.

The processor 10 and the switch unit 20
Since the normality of the interface between the new ACT processor 11 and the new ACT processor 11 is monitored at regular intervals, if it takes a long time to initialize the new ACT processor 11, the switch unit 20 detects an interface abnormality and controls the new ACT processor 11. It will not be accepted.

According to the present invention, the initial setting time at system startup and the switching time at the time of system switching of the switch section are reduced, and the normality of the interface between the processor and the switch section is maintained at the time of system switching of the processor. To realize a communication processing device capable of performing such operations.

[0013]

FIG. 1 is a block diagram for explaining the principle of the present invention. The figure shows a communication processing apparatus. In the figure, reference numerals 10 and 11 denote processors having a duplex configuration for controlling the entire apparatus, and reference numerals 20 and 21 denote cross sections between a plurality of protocol processing units 30 and a plurality of unified line termination units 40. A cross-connect unit 20A for performing a connection process; a line termination control unit 20B for performing a line termination control;
A, a switch unit having a duplex configuration including a control unit 20C that controls the line termination control unit 20B.

Reference numerals 51A and 51B denote write memory interfaces provided in the processors 10 and 11 according to the present invention.
The control information and the connection information of the protocol processing unit 30 and the line terminating unit 40 are transferred from the 0 and 11 to the switch units 20 and 21 collectively.

The reference numeral 60 denotes a switch unit 2 according to the present invention.
A difference detection unit provided in 0 and 21. The control information and connection information transmitted last time, and the control information transmitted this time,
The difference from the connection information is detected.

In the present invention, at the time of initialization, the control information and connection information are transferred from the processors 10 and 11 to the switch units 20 and 21 collectively by the write memory interfaces 51A and 51B. After that, the difference detection unit 60 detects the difference between the current information and the next information of the control information and the connection information from the next time,
By performing only the difference processing, the initial setting and system switching processing can be performed quickly.

Further, by providing the read memory interface 52 in the processors 10 and 11, the connection information in the switch units 20 and 21 and the operation state of the line termination unit 40 can be collectively read from the processors 10 and 11. It becomes possible. (Claims 1 and 2) By providing the maintenance command interface 53 in the processors 10 and 11, it becomes possible to write a maintenance command and read the status corresponding to the maintenance command. (Claim 3) By providing a write memory interface (the write memory interfaces 51A and 51B are collectively referred to as a write memory interface), a read memory interface, and a maintenance command interface, the SB
After writing information to the Y-system switch unit 21, the same information is written to the ACT-system switch unit 20 so that system switching can be performed quickly. When the SBY switch 21 is switched to the ACT switch, the state of the line termination unit 40 is read, and if the control information is different from the control information set by the processors 10 and 11, the line termination unit 40 is reset. Further, when the processor system switching detection unit 70 of the switch units 20 and 21 detects the system switching of the processors 10 and 11, the information set by the old ACT system processor 10 is discarded. (Claim 6) After the processors 10 and 11 write to each interface, the interface monitoring unit 80 monitors the normality of each interface. (Claim 7)

[0018]

FIG. 2 is a block diagram for explaining an embodiment of the present invention. The figure shows a communication control device that includes all the features of claims 1 to 7.

In the figure, reference numerals 10 and 11 denote processors of a duplex configuration for controlling the entire apparatus, and reference numerals 20 and 21 perform cross-connect processing between a plurality of protocol processing units 30 and a plurality of single line termination units 40. A cross-connect unit 20A;
This is a switch unit having a duplex configuration including a line termination control unit 20B that performs line termination control, a cross-connect unit 20A, and a control unit 20C that controls the line termination control unit 20B.

The memory interfaces 50A and 50B are provided in the processors 10 and 11 according to the present invention, and include a write memory interface, a read memory interface, and a maintenance command interface.

Reference numeral 60 denotes a difference detection unit, 70 denotes a processor system switching detection unit, and 80 denotes an interface monitoring unit. FIG. 3 is a diagram illustrating a memory interface according to an embodiment of the present invention. The memory interface 50 of the present invention is provided with the switch units 20 and 21 from the processor 10.
A write memory interface 51 as a state setting area in which all control information and connection information between the protocol processing unit 30 and the line termination unit 40 can be written collectively, and switch connection information in the switch unit 20 And a read memory interface 52 as a status display area from which the operating state of the line terminating unit 40 can be collectively read from the processor 10, a command setting area 53A for setting a command from the processor 10 to the switch unit 20, and a command It comprises a maintenance command interface 53 having a status display area 53B for reading the status from the processor 10.

FIG. 4 is a flowchart (1) of a processor state setting process according to the embodiment of the present invention. With the above configuration, the ACT processor 10 sets the same information in the write memory interfaces 51A and 51B. And
In STEP (hereinafter referred to as S) 1, the ACT processor 10 executes a state setting process on the SBY switch unit 21, and then executes a state setting process on the ACT switch unit 20 in S 2.

FIG. 5 is a flowchart (2) of a processor state setting process according to the embodiment of the present invention.
This shows the processing contents of S2. At the time of initial setting of the communication processing device, the switch units 20 and 21 read all information, and control the switch connection and the line termination unit 40 based on the information.

In step S1, when a status setting write enable notification is received from the switch unit 20, the ACT processor 10 writes the status in the write memory interfaces 51A and 51B in step S2. Then, in S3, a request is made to the switch unit 20 to read the state setting information.
, The processor 10 reads the status setting information written by the switch unit 20 in S6, sends a status display write enable notification to the switch unit 20 in S7, and checks the status display contents in S8. Then, the switch connection and the control of the line termination unit 40 are performed according to the setting information.

FIGS. 6 and 7 are flowcharts (1) for detecting a state setting read request of the switch section according to the embodiment of the present invention.
(2). When the state setting reading is started in S1, the processor 10 notifies the processor 10 that the state setting can be written in S2, and when there is a change in the switch connection information written in S3, the connection of the switch unit 20 is changed in S4. Is performed, and the switch connection information is read in S5. In S6 to S8, it is determined whether or not there is a change in the line control information, and if there is a change, according to the information,
Execute the line control process and read the result. And
In S9, if there is a notice that the status display can be written from the processor 10, the status display is written in S10, and a read request is made to the processor 10 in S11. In S12, the processor 10
The status display reading of the processor 10 is confirmed by the status write enable notification from the CPU 10.

The ACT processor 10 includes a switch unit 2
The information of the status display area is read in accordance with the status processing flowchart for the operation confirmation of 0. When the switch unit 21 of the SBY system is switched to the ACT system, the new AC
The T-system switch unit 21 reads the state of the line termination unit 40 and compares the state with the control information set in the write memory interface 51 from the ACT-system processor 10.
Re-set only the information that is different.

Further, when the processor system switching detecting unit 70 of the switch unit 20 detects the system switching, the write memory interface 51 and the maintenance command interface 5
If the old ACT processor 10 sets the setting information in 3 and there is setting information that has not been processed yet, the setting information is discarded. Thereafter, the processor 11 of the new ACT system writes data into the memory interfaces 50A and 50B, whereby the switch unit 20 recognizes that the initial setting is completed, and starts monitoring the normality of the memory interfaces 50A and 50B.

[0028]

According to the present invention, in the communication processing apparatus, a large amount of control information can be collectively written from the processor to the switch section, so that the command is not edited a plurality of times, and the transfer time can be reduced. Thus, it is possible to reduce the system start-up time.

Similarly, the switch connection information in the switch section and the operation state of the line terminating section can be collectively read from the processor, and the system start-up time can be shortened.

Also, by setting the same information as the ACT system from the processor to the SBY system switch unit, the new ACT system switch unit performs the same control as the old ACT system switch unit at the time of system switching of the switch unit. The state can be continued, and only the frames received during the system switching time are lost, and the loss of frames can be reduced.

Further, it is possible to prevent the control information between the switch unit and the processor from passing each other at the time of system switching of the processor, and to maintain the normality of the interface with the new ACT system processor.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating a memory interface according to an embodiment of the present invention;

FIG. 4 is a flowchart (1) of a processor state setting process according to the embodiment of the present invention;

FIG. 5 is a flowchart (2) of a processor state setting process according to the embodiment of the present invention;

FIG. 6 is a flowchart (1) for detecting a state setting read request of the switch unit according to the embodiment of the present invention;

FIG. 7 is a flowchart (2) for detecting a state setting read request of the switch unit according to the embodiment of the present invention;

FIG. 8 is a block diagram illustrating a conventional communication processing apparatus.

[Explanation of symbols]

 10, 11 Processor 10A, 10B Memory 20, 21 Switch Unit 20A Cross-Connect Unit 20B Line Termination Control Unit 20C Control Unit 30 Protocol Processing Unit 40 Line Termination Unit 50, 50A, 50B Memory Interface 51A, 51B Write Memory Interface 52 Read Memory Interface 53 Maintenance command interface 53A Command setting area 53B Status display area 60 Difference detection unit 70 Processor system switching detection unit 80 Interface monitoring unit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Shuichi Kuniyoshi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hideo Abe 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fujitsu Co., Ltd. (72) Inventor Tadashi Usui Nippon Telegraph and Telephone Co., Ltd. 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo

Claims (7)

[Claims] 1. A switch unit having a duplex configuration including a cross-connect unit for performing a cross-connect process between a plurality of protocol processing units and a plurality of unified line termination units, and a line termination control unit for controlling the line termination unit. And a communication processing device including a redundantly configured processor that controls the redundantly configured switch unit, wherein, in the processor, batch transfer of all control information and connection information of the protocol processing unit and the line termination unit is performed. A write memory interface to perform, and a difference detection unit that detects a difference between control information and connection information sent last time and control information and connection information sent this time is provided in the switch unit. Performs batch transfer of control information and connection information from the processor to the switch unit, and performs all information processing during initial setting. And a communication processing device for performing processing only on difference information detected by the difference detection unit from the next time. 2. The communication processing device according to claim 1, further comprising a read memory interface for batch reading the switch connection information in the switch unit and the operation state of the line termination unit from the processor. Item 2. The communication processing device according to Item 1. 3. The communication processing apparatus according to claim 2, further comprising a maintenance command interface for reading a maintenance command. 4. The communication processing device according to claim 1, wherein the processor is provided with the write memory interface, the read memory interface, and the maintenance command interface, and writes control information and connection information in the switch unit of the standby system, and then writes the current information to the active switch. 2. The communication processing device according to claim 1, wherein the same control information and connection information are written in a switch unit of the system. 5. The communication processing apparatus according to claim 1, wherein when the switch unit of the standby system is switched to the active system, the state of the line termination unit is read, and the read information is different from the control information set from the processor unit. 5. In the case, resetting of the line termination unit is performed.
The communication processing device according to claim 1. 6. The communication processing device according to claim 1, further comprising: a switching unit that includes a processor switching detection unit that detects that the processor has been switched, wherein the switching unit switches processor switching in the processor switching unit. 2. The communication processing apparatus according to claim 1, wherein upon detection, information set by an old active processor is discarded from the write memory interface. 7. The communication processing device according to claim 1, further comprising: an interface monitoring unit that monitors the normality of the write memory interface, the read memory interface, and the maintenance command interface, wherein the processor of a new active system is connected to each of the interfaces. 2. The communication processing apparatus according to claim 1, wherein the initialization of the switch unit is completed by writing to the interface unit, and the normality of each interface is monitored by the interface monitoring unit.