JPH07319788A - Host communication interface board of printer system - Google Patents

Abstract

PURPOSE:To prevent communication with a host from being halfway disconnected by the reset signal supplied to an asynchronous board by temporarily holding the asynchronously inputted reset signal internally and controlling the timing of supply of the reset signal to the inside. CONSTITUTION:When an asynchronously inputted reset signal (a) is held, a sub-CPU 5 stop the communication control performed till then and reports input of the reset signal (a) to a host 4 while controlling a communication control part 8. The sub-CPU s disconnects communication with the most 4 while controlling the communication control part 8, and a communication end signal (f) is transmitted from the communication control part 8 to a reset synchronizing part 9. This part 9 finds the end of communication by the communication end signal (f) to output a synchronous reset signal (e) to each part of a host communication interface board 2. Each part or the most communication interface board 2 to which the synchronous reset signal (e) is inputted, is initialized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication interface board in a printer system connected to a host computer by a communication circuit.

[0002]

2. Description of the Related Art In a control unit of a conventional printer system, as shown in FIG. 4, a central processing board 1 on which a main CPU 3 is mounted, a host communication interface board 2 composed of only logic elements, and a plurality of function boards. 20
-1 to 20-n. In recent years, as the printer system has become faster, it has been required to speed up the print data processing of the control unit of the printer system, and it is not possible to increase the transfer speed and the processing speed with one CPU. It has come to constitute a function distributed type. In this system, the host interface board 2 and each function board 20-1 to 20
The sub CPU 5 is mounted at -n.

(1) Reset Signal The reset signal of the printer system having the function-distributed configuration by the multi-microprocessor shown in FIG. 5 will be described. The reset signal of the printer system in the function distribution type configuration by the multi-microprocessor of FIG. 5 is generated by the central processing unit and supplied to each board. The timing at which the reset signal is output is when the power is supplied to the printer system to initialize the central processing unit, when the main CPU of the central processing unit becomes abnormal and the main CPU is initialized, and when the power of the central processing unit is turned on. Is detected regardless of the operating status of each board when an abnormality (power interruption, voltage drop, etc.) is detected and the main CPU is initialized. In particular, resetting the board on which the CPU is mounted is important, and CP can be reset normally.
If not given to U, the CPU will not operate normally. Therefore,
The board is not initialized properly and the function cannot be realized satisfactorily.

(2) Outline of Communication with Host When the host sends print data to the printer, steps S10 to S14 in the flow of FIG. 8 are performed.
First, a communication circuit is established as shown in FIG. Next comes the phase of transmitting print data from the host to the printer. After the transmission is completed, the communication circuit is released and the communication between the host and the printer ends normally.

(3) An example of the operation of the host interface board Regarding the operation of the host interface board of the printer system in the function distribution type configuration by the multi-microprocessor of FIG. 5, the block diagram of FIG. 7 and FIGS.
This will be described in detail using the flow of No. 11. The communication register 6 is a register that receives a command from the central processing board 1 through the system bus c. When the central processing board 1 writes a command in the communication register 6, the internal sub CP
U5 reads the command from the communication register 6 through the internal bus d.

The sub CPU 5 decodes the received command, and if the received command is a command to transfer print data from the host to the central processing board 1 (hereinafter referred to as a received command), first the host 4 The procedure for establishing communication is read from the memory 11 and steps S20 to S in the flow of FIG.
According to the procedure shown in 25, the communication probability with the host 4 is calculated while controlling the communication control unit 8.

If the communication probability is successful, the procedure for the print data to be transferred from the host 4 is stored in the memory 1.
1 is read, and steps S30 to S in the flow of FIG.
According to the procedure of 37, the host 4 transfers print data while controlling the communication control unit 8. If there is a large amount of print data to be transferred from the host 4, the above procedure is repeated. The print data from the host 4 is
The sub CPU 5 receives from the communication control unit 8 through the communication line b. The sub CPU 5 stores the received print data in the data buffer 12. Data buffer 1
When the print data is accumulated, the data 2 transfers the print data to the central processing unit 1 through the system bus c.

When there is no print data to be transferred from the host 5, the sub CPU 5 reads out the procedure for releasing the communication circuit from the memory 7, and controls the communication control unit 8 according to the procedure of steps S40 to S45 in the flow of FIG. While controlling, the communication with the host 4 is cut off, and a series of communication ends as shown in the timing chart of FIG.

(4) Abnormal Processing When the host wants to send print data to the printer, the host first requests the host communication interface board of the printer to receive print data as in the flow of FIG. When the internal sub CPU 5 is operating normally, it responds to the request with Ready or Busy as shown in the timing chart of FIG. The host responded with Busy terminates abnormally after several tries. After that, the cause of the abnormal termination is investigated while communicating with the printer as in the procedure of steps S50 to S53 in the flow of FIG. If the printer is out of paper and cannot receive it, the printer reports the out-of-paper information to the host via communication. The host in which the cause of the communication abnormality is found out is notified to the operator by a predetermined method, and the operator waits for processing. When an abnormality occurs in the processing process of the CPU in this way, the CPU performs a predetermined abnormality processing as in Japanese Patent Publication No. 19574/1993.

However, when a reset is input to the internal sub CPU of the host communication interface board which controls the communication during the communication of the print data, as shown in FIG.
When a reset is input as shown in the operation timing chart of FIG. 4, the board is initialized. Therefore, it is not possible to respond to communication from the host during initialization after the reset is input. Therefore, if there is a print data reception request from the host during the initialization, the board internal sub CPU cannot respond to the host. If no response is received from the communication interface board, the host interrupts a series of communication and forcibly releases the communication line if there is no response even after waiting for a certain time. Then, the host repeats again from the beginning according to the flow of FIG. 8, but since the power supply of the board is cut off, the host cannot respond and the host repeats the same procedure until the board becomes ready to respond to the host. There is also a host that unilaterally judges from the above communication sequence that the printer is inoperable = power-off state if there is no response from another host once again starting from the beginning.

[0011]

Generally, when a function distribution type with a multi-microprocessor such as a printer system of recent years is used, the above-mentioned reset output from the central processing unit is caused by the internal CPU operation of each board. Since it is supplied to each board asynchronously, there is no problem even if a reset signal is supplied asynchronously with the internal state among the supplied boards, but some boards like the host communication interface board. In some boards, if a reset is input during communication with the host, the host communication is forcibly interrupted and the board initialization starts.
In that case, the host whose communication is interrupted midway tries to establish communication again, but the CP of the communication interface board
Since U is in the process of initialization, the CPU cannot respond to the communication from the host, and the host repeats from the beginning many times, and in some cases, the host once decided to shut down the power.

[0012]

The host communication interface board of the present invention comprises a reset synchronization section.

[0013]

The reset signal input asynchronously with the board is temporarily held by the reset synchronization section, and is internally synchronized at the timing at which the communication state is not abnormal even if the internal CPU is reset, as shown in the operation timing chart. Since the reset signal can be output to the CPU, the reset signal supplied to the asynchronous board prevents the communication with the host from being interrupted midway.

[0014]

1 is a block diagram showing an example of a host communication interface board of the present invention, FIG. 2 is a circuit diagram showing an example of a synchronizing section of the host communication interface board of the present invention, and FIG. 3 is an operation of the present invention. 2 is a timing chart of. First, a series of communications for normally receiving print data from the host according to the present invention will be described. The host interface board of the present invention includes a communication register 6, a sub CPU 5,
The communication control unit 8 and the reset synchronization unit 9 are provided. The communication register 6 is a register that receives a command from the central processing board 1 through the system bus. When the central processing board 1 writes a command in the communication register 6, the internal sub CPU 5 receives the command through the internal bus d.

The sub CPU decodes the received command, and if the received command is a command to transfer print data from the host to the central processing board 1 (hereinafter referred to as a received command), first the host 4 The procedure for establishing communication is read from the memory 11 and communication is established with the host 4 while controlling the communication control unit 8 according to the procedure. When the communication is successfully established, the procedure for transferring the print data from the host 4 is read from the memory 11 and the host 4 transfers the print data while controlling the communication control unit 8 according to the procedure. If there is a large amount of print data to be transferred from the host 4, the above procedure is repeated. The print data from the host is received by the sub CPU 5 from the communication control unit 8 through the communication line b.

The sub CPU 5 stores the received print data in the data buffer 12. The data buffer 12 is used by the central processing unit 1 when print data is accumulated.
The print data is transferred to the system via the system bus c. When there is no print data to be transferred from the host 5, the sub CPU 5 reads out from the memory 11 a procedure for communication disconnection, and follows the procedure, the communication control unit 8
The communication with the host 4 is cut off while controlling the.

Next, the operation when the reset signal is supplied to the board of the present invention will be described. When the reset of the central processing board 1 is generated and the reset signal a is input to the main board until the above-mentioned (1) to (3) are completed, the reset synchronization unit 9 temporarily holds the reset signal. , The communication control unit 8 is notified by the hold signal h. The sub CPU 5 controlling the communication control unit 8 knows indirectly that the reset signal a is held from the communication control unit 8.

When the sub CPU 5 knows that the reset signal a is held, it cancels the communication control so far and reads out the reset signal input procedure from the memory 11 and resets it to the host 4 while controlling the communication control section 8 according to the procedure. Signal that signal a has been input. When the host 4 has been notified that the reset signal a has been normally input, the above procedure is performed. When the normal processing is completed, the communication control unit 8 transmits the communication end signal f to the reset synchronization unit 9. When it is determined that the communication is completed by the communication end signal f, the set synchronization unit 9 outputs the synchronization reset signal e to each unit of the board. Sub-CP to which synchronous reset signal e is input
U5 executes initialization of each part of the board.

In the case of the conventional communication interface board, the communication with the host 4 was immediately disconnected without being aware of the communication between the host 4 and the host communication interface board. As described above, it is necessary to perform a scan for trying to establish communication again and again spending a long time. However, even if this board is supplied with the reset signal a, it is temporarily held by the reset synchronization unit 9 and notifies the host 4 that the reset signal a has been supplied, and outputs the synchronous reset signal e to each internal unit after the end of communication. , The communication with the host 4 can be normally terminated immediately without interruption. Therefore, since the above operation is not performed, there is an effect that the communication line b and the host 4 can be effectively used.

[0020]

As described above, according to the present invention, since the communication is interrupted halfway through the reset input, the host does not respond from the communication interface board and repeats the procedure from the beginning again and again. I didn't finish even if I hit it, or I once decided that the power was cut off. But,
This board can internally hold the reset signal input asynchronously and control the timing to supply the reset signal internally, so suddenly interrupt the communication by the reset input during the communication with the host. Instead of reporting the reason for communication cutoff to the host and then ending communication, the host has the characteristic that the reason for the cutoff can be accurately known without the need for the procedure necessary for disconnecting the communication line. Further, since the conventional procedure is unnecessary, there is an effect that the communication line and the host can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram of a host communication interface board of the present invention.

FIG. 2 is a reset holding circuit.

FIG. 3 is a timing chart showing the operation of the present invention.

FIG. 4 is a block diagram of a conventional printer system.

FIG. 5 is a block diagram of a conventional printer system.

FIG. 6 is a block diagram of a conventional communication interface board.

FIG. 7 is a block diagram of a conventional communication interface board.

FIG. 8 is a flowchart showing a communication procedure.

FIG. 9 is a flowchart showing a communication procedure.

FIG. 10 is a flowchart showing a communication procedure.

FIG. 11 is a flowchart showing a communication procedure.

FIG. 12 is a flowchart showing a communication procedure.

FIG. 13 is a timing chart showing a conventional operation.

FIG. 14 is a timing chart showing a conventional operation.

[Explanation of symbols]

1 central processing board, 2 host communication interface board, 3 main CPU, 4 host, 5
Sub CPU, 6 communication registers, 8 communication control unit,
9 Reset synchronization unit, 11 memory, 12 data buffers, 20 ₁ -20n function board, a
Reset signal, b communication line, c system bus,
d internal bus, e synchronous reset signal, f communication end signal, g communication data, h hold signal.

Claims (1)

[Claims] 1. A communication interface board of a printer, which receives print data from a host using a communication line, and a communication register for receiving a predetermined command from a central processing board of a printer system through a system bus; Connected to the host by a communication line, the sub CPU performing communication control according to the command received in step 1, the memory holding the communication procedure to be executed by the sub CPU, and the sub CPU reading from the memory. A communication control unit that controls a communication line according to the applicable communication procedure, and after holding and storing print data from the host,
A communication interface board that is equipped with a data buffer that transfers to the central processing unit and a reset synchronization unit that outputs an asynchronous reset signal from the printer system to each part of the board in synchronization with the operating status inside the board.