JP3465343B2 - Printer system host communication interface board - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication interface board in a printer system connected to a host computer by a communication circuit. 2. Description of the Related Art As shown in FIG. 4, a control unit of a conventional printer system includes a central processing board 1 on which a main CPU 3 is mounted, a host communication interface board 2 composed of only logic elements, and a plurality of control boards. Function board 20
-1 to 20-n. In recent years, with the increase in the speed of the printer system, the speed of print data processing in the control unit of the printer system has been demanded, and the transfer speed and the processing speed cannot be increased with one CPU. It has come to constitute a function-distributed type. In this system, the host interface board 2 and each function board 20-1 to 20
At -n, the sub CPU 5 is mounted. (1) Reset signal A reset signal of a printer system in a function-distributed configuration using a multi-microprocessor shown in FIG. 5 will be described. The reset signal of the printer system in the function distribution type configuration using the multi-microprocessor of FIG. 5 is generated by the central processing unit and supplied to each board. The reset signal is output when the power is supplied to the printer system to initialize the central processing unit, when the main CPU of the central processing unit becomes abnormal and the main CPU is initialized, and when the power of the central processing unit is initialized. Is output regardless of the operation status of each board when the main CPU is initialized by detecting an abnormality (power interruption, voltage drop, etc.). In particular, it is important to reset the board on which the CPU is mounted.
Unless given to U, the CPU does not operate normally. Therefore,
The board is not initialized properly and the function cannot be realized satisfactorily. (2) Outline of communication with the host When the host transmits print data to the printer, steps S10 to S14 in the flow of FIG.
First, a communication circuit is established as shown in FIG. Next, it is a phase of transmitting print data from the host to the printer. After the transmission is completed, the communication circuit is released, and the communication between the host and the printer ends normally. (3) One example of operation of host interface board Regarding the operation of the host interface board of the printer system in the function distributed type configuration using the multi-microprocessor of FIG. 5, the block diagram of FIG.
This will be described in detail with reference to the flow of FIG. The communication register 6 is a register that receives a command from the central processing board 1 via the system bus c. When the central processing board 1 writes a command to the communication register 6, the internal sub CP
U5 reads a command from the communication register 6 through the internal bus d. The sub CPU 5 decodes the received command, and if the received command is a command to transfer print data from the host to the central processing board 1 (hereinafter referred to as a received command), first, the sub CPU 5 The procedure for establishing communication is read from the memory 11 and steps S20 to S20 in the flow of FIG.
According to the procedure shown in 25, the communication probability with the host 4 is determined while controlling the communication control unit 8. [0007] If the communication probability is successful, the procedure to have the host 4 transfer the print data is stored in the memory 1.
1 and read out from steps S30 to S30 in the flow of FIG.
According to the procedure of 37, the print data is transferred from the host 4 while controlling the communication control unit 8. If there is much print data to be transferred from the host 4, the above procedure is repeated. The print data from the host 4 is
The sub CPU 5 receives from the communication control unit 8 through the communication line b. The sub CPU 5 stores the received print data in the data buffer 12. Data buffer 1
2 transfers the print data to the central processing unit 1 via the system bus c when the print data is accumulated. When there is no more print data to be transferred from the host 5, the sub CPU 5 reads out the procedure to release the communication circuit from the memory 7, and controls the communication control unit 8 in accordance with the procedures of steps S40 to S45 in the flow of FIG. Under control, the communication with the host 4 is cut off, and a series of communication ends as shown in the timing chart of FIG. (4) Abnormal processing When the host wants to send print data to the printer, the host first requests the host communication interface board of the printer to receive print data as shown in the flow of FIG. When the internal sub CPU 5 is operating normally, it responds to the request with Ready or Busy as shown in the timing chart of FIG. The host responded with Busy ends abnormally after trying several times. Thereafter, an investigation into the cause of the abnormal termination is performed while communicating with the printer as in steps S50 to S53 of the flow of FIG. If the printer is out of paper and cannot receive it, the printer reports out-of-paper information to the host by communication. The host that has determined the cause of the communication abnormality is notified to the operator by a predetermined method, and waits for processing by the operator. When an abnormality occurs during the processing of the CPU, the CPU performs a predetermined abnormality process as disclosed in Japanese Patent Publication No. 3-19574. However, when a reset is input to the internal sub CPU of the host communication interface board which controls the communication during the communication of the print data, FIG.
As shown in the operation timing chart shown in FIG. 4, when a reset is input, the board is initialized, so that it cannot respond to communication from the host during the initialization after the reset is input. Therefore, if there is a print data reception request from the host during the initialization, the board internal sub CPU cannot respond to the host. If there is no response from the communication interface board after a certain period of time, if there is no response, the host suspends a series of communication and forcibly releases the communication line. Then, the host repeats the procedure again from the beginning according to the flow of FIG. 8, but since the power supply of the board is cut off, the host cannot respond and the same procedure is repeated until the board can respond to the host. In addition, there is a host in which another host re-starts from the beginning only once, but if there is no response, the printer is unilaterally determined to be inoperable state = power-off state through the above communication sequence. [0011] In general, when a function distribution type using a multi-microprocessor is used as in a recent printer system, the above-mentioned reset output from the central processing unit is reset inside each board. Since it is supplied to each board asynchronously with the CPU operation, some of the supplied boards do not have any problem even if a reset signal is supplied asynchronously with the internal state, but some host communication interface boards In some boards, when a reset is input during communication with the host, the communication between the host is forcibly interrupted in the middle and the initialization of the board is started.
In this case, the host whose communication is interrupted on the way tries to establish communication again, but the CP of the communication interface board
Since U is performing initialization, the CPU cannot respond to communication from the host, and some hosts may repeat the operation from the beginning many times, or some hosts may determine that the power is cut off. A host communication interface board according to the present invention includes a reset synchronization section. The reset signal input asynchronously with the board is temporarily held in the reset synchronizing section, and the internal synchronizing is performed at a timing at which no abnormality occurs in the communication state even when the internal CPU is reset. As shown, since the reset signal can be output to the CPU, the communication with the host is prevented from being interrupted on the way by the reset signal supplied to the asynchronous board. FIG. 1 is a block diagram showing an example of a host communication interface board of the present invention, FIG. 2 is a circuit diagram showing an example of a synchronizing section of the host communication interface board of the present invention, and FIG. 6 is a timing chart of the operation of the invention. First, a series of communications for normally receiving print data from a host according to the present invention will be described. The host interface board of the present invention includes a communication register 6, a sub CPU 5,
A communication control unit 8 and a reset synchronization unit 9 are provided. The communication register 6 is a register for receiving a command from the central processing board 1 through a system bus. When the central processing board 1 writes a command in the communication register 6, the internal sub CPU 5 receives the command through the internal bus d. The sub CPU decodes the received command. If the received command is a command to transfer print data from the host to the central processing board 1 (hereinafter referred to as a received command), the sub CPU first A procedure for establishing communication is read from the memory 11 and communication with the host 4 is established while controlling the communication control unit 8 according to the procedure. If the communication is successfully established, the host 4 reads the procedure for transferring the print data from the memory 11 and controls the communication control unit 8 to transfer the print data according to the procedure. If there is much print data to be transferred from the host 4, the above procedure is repeated. The sub CPU 5 receives the print data from the host from the communication control unit 8 through the communication line b. The sub CPU 5 stores the received print data in the data buffer 12. The data buffer 12 stores the central processing unit 1 when print data is accumulated.
Is transferred via the system bus c. When there is no more print data to be transferred from the host 5, the sub CPU 5 reads out the procedure to disconnect the communication from the memory 11 and follows the procedure according to the procedure.
While disconnecting the communication with the host 4. Next, the operation when a reset signal is supplied to the board of the present invention will be described. When a reset is generated under the condition that the reset of the central processing board 1 occurs until the above-mentioned is completed, and the reset signal a is input to the board, the reset synchronizing unit 9 temporarily holds the reset signal. Is notified to the communication control unit 8 by a holding signal h. The sub CPU 5 controlling the communication control unit 8 knows from the communication control unit 8 that the reset signal a is held indirectly. When the sub CPU 5 knows that the reset signal a has been held, the sub CPU 5 terminates the communication control up to now and reads the reset signal input procedure from the memory 11 and resets the host 4 while controlling the communication control unit 8 according to the procedure. Notifies that signal a has been input. When the host 4 is informed that the reset signal a has been input normally, the above procedure is performed. When the normal processing is completed, a communication end signal f is transmitted from the communication control unit 8 to the reset synchronization unit 9. When the communication end signal f indicates that the communication has been completed, the set synchronization section 9 outputs a synchronization reset signal e to each section of the board. Sub CP to which synchronous reset signal e is input
U5 initializes each part of the board. In the case of the conventional communication interface board, the communication with the host 4 is immediately disconnected without being aware of the communication between the host 4 and the host communication interface board. As described above, it is necessary to perform a scan that attempts to establish communication again and again over a long time. However, even if the reset signal a is supplied, the board temporarily holds the reset signal a by the reset synchronizing unit 9 and notifies the host 4 that the reset signal a has been supplied, and outputs the synchronous reset signal e to each internal unit after the communication is completed. Thus, the communication with the host 4 can be normally and promptly terminated without interruption. Therefore, since the above operation is not performed, there is an effect that the communication line b and the host 4 can be used effectively. According to the present invention, since the communication has been interrupted on the way due to the input of the reset until now, the host does not receive a response from the communication interface board, and the procedure from the beginning over and over again is repeated. Repeatedly, it did not end even after a long time, and it was once judged that the power was cut off. But,
Since this board can temporarily hold the reset signal input asynchronously and control the timing of supplying the reset signal internally, suddenly interrupt the communication by reset input during communication with the host However, since the communication is terminated after reporting the reason for the communication interruption to the host, the host does not need to perform the necessary procedure when the communication line is interrupted as in the past, so that the host can know the reason for the interruption accurately. In addition, there is an effect that the communication line and the host can be used effectively because the conventional procedure is unnecessary.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a host communication interface board of the present invention. FIG. 2 is a reset holding circuit. FIG. 3 is a timing chart showing the operation of the present invention. FIG. 4 is a block diagram of a conventional printer system. FIG. 5 is a block diagram of a conventional printer system. FIG. 6 is a block diagram of a conventional communication interface board. FIG. 7 is a block diagram of a conventional communication interface board. FIG. 8 is a flowchart showing a communication procedure. FIG. 9 is a flowchart showing a communication procedure. FIG. 10 is a flowchart showing a communication procedure. FIG. 11 is a flowchart showing a communication procedure. FIG. 12 is a flowchart showing a communication procedure. FIG. 13 is a timing chart showing a conventional operation. FIG. 14 is a timing chart showing a conventional operation. [Description of Signs] 1 Central processing board, 2 Host communication interface board, 3 Main CPU, 4 Host, 5
Sub CPU, 6 communication register, 8 communication control unit,
9 Reset synchronization unit, 11 memory, 12 data buffers, 20 ₁ -20n function board, a
Reset signal, b communication line, c system bus,
d Internal bus, e Synchronous reset signal, f Communication end signal, g Communication data, h Hold signal.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13/00 G06F 3/12

Claims (1)

(57) [Claim 1] In a communication interface board of a printer device for receiving print data from a host using a communication line, a predetermined command is sent from a central processing board of the printer system through a system bus. A communication register that receives the command, a sub-CPU that performs communication control according to the command received by the communication register, a memory that holds a communication procedure to be executed by the sub-CPU according to the command, and a host and a communication line, A communication control unit for controlling a communication line in accordance with a corresponding communication procedure read from the memory by the sub CPU, a data buffer for holding and accumulating print data from the host, and then transferring the print data to a central processing unit; Outputs a reset signal from the system to each part of the board. A communication interface board comprising a reset synchronizer to reset the synchronization unit temporarily holds the reset signal when the reset signal to the communication interface board is input, the sub-C was learned that the reset signal is held
A communication interface board which outputs a reset signal to each part of the board after the PU notifies the host that a reset signal has been input and terminates communication with the host.