JPS5856317A - Manufacture of semiconductor thin film - Google Patents

Manufacture of semiconductor thin film

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Publication number
JPS5856317A
JPS5856317A JP56153743A JP15374381A JPS5856317A JP S5856317 A JPS5856317 A JP S5856317A JP 56153743 A JP56153743 A JP 56153743A JP 15374381 A JP15374381 A JP 15374381A JP S5856317 A JPS5856317 A JP S5856317A
Authority
JP
Japan
Prior art keywords
thin film
semiconductor thin
semiconductor
film
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56153743A
Other languages
Japanese (ja)
Inventor
Kazumichi Omura
大村　八通
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56153743A priority Critical patent/JPS5856317A/en
Publication of JPS5856317A publication Critical patent/JPS5856317A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form the solid-phase grown semiconductor crystal thin film accompanying no fusion and soidification by a method wherein a processing is performed on a groove of shallow depth or a protruded structure formed on the suface of an insulated substrate while an amorphous semicondutor thin film is deposited on said substrate, and heat treatment is performed thereon. CONSTITUTION:An oxide film 2 is formed by steam-oxidizing a (100) Si wafer 1. A resist pattern extending in one direction is then formed by applying resist 3 and performing exposure and developing processes. Then, an SiO2 film is etched by performing a reactive ion-etching using the resist as a mask. Said wafer 1 is placed in a vacuum deposition device and Si4 is vapor-deposited. After the vapor-deposition process has been finished, the interior of the vapor-deposition device is heated up under vacuum. A wafer 1 is then picked out and heated in an N2 atmosphere.

Description

【発明の詳細な説明】 本発明は絶縁基板上の半導体薄膜に関し％特にすぐれた
キャリア易動度を有する半導体薄膜の製造方法ＶＣＷａ
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor thin film on an insulating substrate.
do.

絶縁基板上の半導体結晶薄膜は８０８　（サファイア上
のシリコン）の例でも判るように次のような利点を有す
る。すなわち■薄膜を島状に分離し又は誘電体分離によ
抄素子間の分離が容易且つ完全に出来る。■拡散拳イオ
ン注入等で不純物を絶縁膜界面まで導入すｂときはＰ−
ｎ接合の面積を著しく小さく出来るため浮遊容量が従っ
て小さく、高速動作が可能。■この薄膜上ＫＭＯＳイン
ノ｛−タを作るときは基板バイアス効果がないことから
スイッチング速度が大きい等である。この他、絶縁基板
上の半導体薄膜は半導体素子の三次元化ということで注
目されている。A semiconductor crystal thin film on an insulating substrate has the following advantages, as shown in the example of 808 (silicon on sapphire). That is, (1) separating the thin film into islands or dielectric separation makes it possible to easily and completely separate the elements; ■When introducing impurities to the insulating film interface by diffusion fist ion implantation, etc., P-
Since the area of the n-junction can be significantly reduced, stray capacitance is therefore small and high-speed operation is possible. (2) When making this thin-film KMOS inverter, there is no substrate bias effect, so the switching speed is high. In addition, semiconductor thin films on insulating substrates are attracting attention because they enable three-dimensional semiconductor devices.

すかわち、半導体単結晶基板上に半導体素子を構成した
後、その表面を誘電体絶縁薄膜でおおい。That is, after a semiconductor element is formed on a semiconductor single crystal substrate, its surface is covered with a dielectric insulating thin film.

これを絶縁基板としてこの上に半導体結晶膜を積み重ね
るととＫよりこの結晶膜に半導体素子を製作出来る。こ
れを繰返すことｋよ９半導体素子は三次元的に集積され
石。所でこのような利点を有する絶縁基板上の半導体結
晶膜ｌ！Ｉｌは従来次のような方法で作られていた。す
なわち絶縁基板上ｒｃ半導体薄膜を堆積し、Ｃｗ、Ａｒ
　′５ｔ、ｉ！　Ｋｒ　ｖ−ザービームを細く絞り半導
体薄膜上に集束させこれをラスタースキャンする、或は
同じ（Ｃｗ電子ビームを洞様に用いる等である。If this is used as an insulating substrate and a semiconductor crystal film is stacked thereon, a semiconductor element can be fabricated on this crystal film using K. By repeating this, the 9 semiconductor elements are integrated three-dimensionally into a stone. By the way, a semiconductor crystal film l on an insulating substrate has such advantages! Conventionally, Il was produced by the following method. That is, an rc semiconductor thin film is deposited on an insulating substrate, and Cw, Ar
'5t, i! A Kr v laser beam is narrowly focused onto a semiconductor thin film and raster scanned, or the same method is used (such as using a Cw electron beam in a sinusoidal manner).

この際、絶縁基板に浅い溝構造をエツチングによって作
っておく。このよう表エネルギービームの走査照射によ
シ半導体薄膜中には数十μｍもの粒径の結晶粒が出来、
このような半導体結晶膜に形成した素子例えばＳｔ結結
晶膜膜上ｎチャネルＭＤＳトランジスタではその電子の
電界効果易動度μＦＫは２００−４００ｃｉｌ！／ｖ　
Ｓｅｅと、バルク（１００）　８ｉの場合の半分程度に
達する。このような別結晶膜を透過電子顕微鏡で調べて
みると溝の辺Ｙ−沿って結晶主軸に近い方向が出現して
いることが判っている。特に絶縁基板の溝構造を反応性
イオンエツチング（ＲＩＥ）などで加工した場合のよう
に鋭い端を持つ場合に顕著な現象である。溝構造が例え
ば９伊に直交する場合は従って（１００）面に近い面を
持つ大結晶粒が発生し、これＫより電子易動度が高いも
のと考えられる。At this time, a shallow groove structure is created in the insulating substrate by etching. Due to this scanning irradiation with the surface energy beam, crystal grains with a grain size of several tens of micrometers are formed in the semiconductor thin film.
In an element formed on such a semiconductor crystal film, for example, an n-channel MDS transistor on a St crystalline film, the electron field effect mobility μFK is 200-400 cil! /v
See and bulk (100) It reaches about half of the case of 8i. When such a separate crystalline film is examined using a transmission electron microscope, it is found that a direction close to the main crystal axis appears along side Y- of the groove. This phenomenon is particularly noticeable when the groove structure of an insulating substrate has sharp edges, such as when processed by reactive ion etching (RIE). If the groove structure is perpendicular to, for example, the (9) plane, large crystal grains with planes close to the (100) plane are generated, and this is thought to have higher electron mobility than the (100) plane.

このような半導体結晶薄膜でも詳細に調べると次のよう
な欠点を有することが判つ九。す々わちゲート長、ゲー
ト巾がいづれも５０μｍ１１度より小さい素子では易動
度の値にバラツキが大きく、易動度の小さい素子がウェ
ハ上でエネルギービームの走査方向ｔｌｃｆａって分布
している。更にこれら素子の酸化膜厚が小さくなるとこ
れら走査方向に分布する素子では酸化膜の耐圧が著しく
悪く危る。When such semiconductor crystal thin films are examined in detail, they are found to have the following drawbacks9. In other words, for devices whose gate length and gate width are both smaller than 50 μm and 11 degrees, there is a large dispersion in mobility values, and elements with small mobility are distributed on the wafer in the scanning direction of the energy beam tlcfa. . Furthermore, as the oxide film thickness of these elements becomes smaller, the withstand voltage of the oxide film becomes extremely poor and dangerous in these elements distributed in the scanning direction.

これらの素子が作られた部分の半導体結晶薄膜を透過電
子顕微鏡や走査形電子顕微鏡で詞ぺることにより次のよ
うな事実が判った。このような箇所はエネルギービーム
走向中のへり付近でありと＼では結晶粒も小さく、且つ
表面に凹凸がある。この凹凸は絶縁性基板に形成した溝
構造とは関係なく、半導体が溶融、固化を打力うときの
物質移動によるものであることが判った。これは液相成
長によ抄結晶粒増大を行なうエネルギービーム照射法に
本質的な特徴である。By examining the semiconductor crystal thin films in which these devices were made using a transmission electron microscope or a scanning electron microscope, the following facts were discovered. Such a location is near the edge of the energy beam, where the crystal grains are small and the surface is uneven. It has been found that these irregularities have nothing to do with the groove structure formed in the insulating substrate, but are caused by mass transfer when the semiconductor is melted and solidified. This is an essential feature of the energy beam irradiation method, which increases the size of paper grains by liquid phase growth.

本発明はこのような事情に鍾みてなされたもので、溶融
・固化を伴なわない固相成長で行わしめゐことを・特徴
とする。The present invention has been developed in view of these circumstances, and is characterized in that it is performed by solid phase growth without melting or solidification.

本発明の方法を以下実施例で説明する。The method of the present invention will be explained in the following examples.

実施例１．（Ｚｏｏ）８１ウエハｌをスチーム酸化して
ＩＰｎ厚の酸化膜２を成長させた０次にレジスト３を塗
布、露光、現像して第１図（り　、　（ｅ）のよう表断
面をもち一方向に延びたレジストパターンを形成する。Example 1. (Zoo) 81 wafer 1 was steam oxidized to grow an oxide film 2 with a thickness of IPn.A resist 3 was applied, exposed, and developed to form a surface cross section as shown in Figure 1 (ri, (e)). A resist pattern extending in the direction is formed.

次にＲＩＥによシレジストをマスクとして８ｔ０１を。Next, I applied 8t01 to RIE using the resist as a mask.

４．ｏｏＡエッチする。第１図（ｂ）　、　（ｆ）。4. ooA have sex. Figure 1 (b), (f).

ＲＩＢは方向性があるのでレジスト除去後の溝構造の稜
は極めて鋭い端とまっている０次にこのウェハを真空蒸
着装置に入れ〜２　Ｘ　１０　’Ｔｏｒｒの真空中で８
ｉ４を３０００人蒸着した。第１図（ｃ）　、　（ｇ）
。Since RIB has directionality, the edges of the groove structure after removing the resist are extremely sharp. Next, this wafer is placed in a vacuum evaporation apparatus ~ 8 in a vacuum of 2 x 10' Torr.
3000 people deposited i4. Figure 1 (c), (g)
.

蒸着速度は４０λ／＠ｅｃ、ウニ・・は蒸着源に対向し
て、自転および公転に近い回転をさせながら蒸着を行な
い、溝構造の側面にもよく蒸着されるよう圧した。蒸着
後装置内真空中で３５０℃に加熱した。ウェハを取り出
し、次に馬響囲気中で５５０℃で７２時間、更に１００
０℃で１時間熱処理した。この薄膜のＴＥＭ観察を行な
った所、アモルファス８ｉは結晶化しており、゛溝構造
の端から結晶化が始っており且膜面―直方向に＜１００
＞方向に近い方向の結晶粒が多いことが判明した。結晶
粒は大きく、その粒径は１〜５μｍに分布している。The vapor deposition rate was 40λ/@ec, and the sea urchin... was vapor-deposited while facing the vapor deposition source while rotating near its own axis and revolution, and pressure was applied to ensure good vapor deposition on the side surfaces of the groove structure. After vapor deposition, the device was heated to 350° C. in a vacuum. The wafer was removed and then incubated at 550°C for 72 hours and then for 100
Heat treatment was performed at 0°C for 1 hour. TEM observation of this thin film revealed that amorphous 8i was crystallized, with crystallization starting from the edge of the groove structure, and with an angle of <100 in the direction perpendicular to the film surface.
It was found that there were many crystal grains in directions close to the > direction. The crystal grains are large, and the grain size is distributed in the range of 1 to 5 μm.

この溝構造の低い部分にチャネル長さ５μ、チャネル巾
１０μのｎチャネルトランジスタを形成した。第１図（
ｄ）。その電子のμ■は４インチウエノ・内の平均が３
１０　Ｃ１ｌ／ｖ　ｓｅｃ　標準偏差は２５ｍ／マｓｅ
ｅであった。上記の代りに従来の通り、Ａｒレーザーを
７０μｍφに絞り１０ｃｌＩＬ／　ｓｅｃの速度で走査
した。この場合には８ｉ薄膜を蒸着でなく低温のＣＶ　
ＤＢｉ膜を用いた。すなわちＳｉＨ４を、上記の表面加
工を施した７００℃の基板上で熱分解してＳＲ膜を堆積
させた。　Ａｒレーザーはその出力をフ〜１２Ｗに変化
させた。結晶粒径は０．５〜１μｍＫ分布していた。同
じく上記と同様のｎチャネルトランジスタを製作し測定
した所、４インチウエノ・内の平均は２９０ｄ／ｖｓｅ
ｃであるが標準偏差は約５０　ｃ１ｔ／ｙ　＠６ｃ　　
であり上述の通りゲート耐圧の悪いものが存在していた
。An n-channel transistor having a channel length of 5 μm and a channel width of 10 μm was formed in the lower part of this groove structure. Figure 1 (
d). The average μ■ of the electron is 3 within 4 inches
10 C1l/v sec Standard deviation is 25m/msec
It was e. Instead of the above, the Ar laser was focused to 70 μm in diameter and scanned at a speed of 10 clIL/sec as before. In this case, the 8i thin film is not deposited by vapor deposition but by low-temperature CV.
A DBi film was used. That is, SiH4 was thermally decomposed on a substrate at 700° C. which had been subjected to the above-mentioned surface treatment, and an SR film was deposited thereon. The Ar laser varied its power to ~12W. The crystal grain size was distributed from 0.5 to 1 μmK. When I fabricated and measured an n-channel transistor similar to the one above, the average value within a 4-inch Ueno was 290d/vse.
c, but the standard deviation is about 50 c1t/y @6c
As mentioned above, there were some with poor gate breakdown voltage.

実施例２．８１ウエハ上に８１Ｈ４とＮＨｓの熱分鵡に
よｆｉ８１．Ｎ４膜を３００ＯＡ堆積した。前と同様に
レジストをマスクとし−ｔ”ＲＩｌｌｆｆ：！す３００
　Ａ８１．Ｎ４膜をエッチした。今回は巾３μｍの突出
部が３０μｍ×２０μｍ　の凹部な囲むようＫ（第３図
）した。Example 2. Fi81. A N4 film was deposited at a thickness of 300 OA. As before, use the resist as a mask -t”RIllff:!300
A81. The N4 film was etched. This time, the protrusion with a width of 3 μm was arranged so as to surround the concave portion with dimensions of 30 μm x 20 μm (Fig. 3).

前述の如（８１を蒸着し、蒸着装置内で３５０℃に加熱
後、Ｓけを５０ＫＶおよび２５０ＫＶで夫々２×１ｏ１
＠／ｃｄイオン注入した。この試料なＮ、中で５５０℃
で７２時間、更Ｋ１００Ｏ℃で１時間熱処理した。とＯ
試料の３０ｐｍＸ２０．ｍｍｏ部分にチャネル長５μｍ
１チャネル巾１０μｍのｎｅｃｈｉｎｎｅ１Ｍ０８トラ
ンジスタを形成した。このトランジスタの電子のμｒ冨
は４インチウエノ・内で平均３３０ｄ／ｖｓｅｃｓ標準
偏差は２２　ｃｓｌ／ｙ　ｌ　ｅ　ｃであった。熱処理
の代シに電子ビームを照射した。すなわち５ＫＶ。As described above (depositing 81 and heating to 350°C in the evaporator, S was heated to 2×1o1 at 50KV and 250KV, respectively).
@/cd ions were implanted. This sample was heated to 550°C in N.
The sample was heat-treated at 100° C. for 72 hours and then at 100° C. for 1 hour. and O
30pm x 20. Channel length 5μm in mmo part
A nechinne1M08 transistor with a channel width of 10 μm was formed. The electron μr value of this transistor was 330 d/v sec on average within 4 inches, and the standard deviation was 22 csl/y le c. Instead of heat treatment, an electron beam was irradiated. That is 5KV.

２ｍＡの電子ビームを６０．ａｍ−に絞り１２ｃｓ／　
５ｅｃＯ線速度で走査した。この際の堆積Ｓｔは前同様
低温のＣＶ　Ｄ８ｉを用いた。この方法で得られた同様
のトランジスタの電子易動度μＦＫは２９０ｃｌｌ／　
ｖ　ｓｅｃ＋標準偏差は４５ｃＩｉ／ｖ　ｓｅｃであっ
た。この試料の表面を走査電子顕微鏡で観察した所電子
ビーム走査１ｉ　ｔｉｃ　Ｇって波状の起伏が認められ
明らかに薄膜は溶融・固化したことが判った。2 mA electron beam at 60. Aperture to am-12cs/
Scanning was performed at a linear velocity of 5ecO. As for the deposition St at this time, low-temperature CV D8i was used as before. The electron mobility μFK of a similar transistor obtained using this method is 290 cll/
v sec + standard deviation was 45 cIi/v sec. When the surface of this sample was observed with a scanning electron microscope, it was found that wavy undulations were observed in electron beam scanning 1 tic G, indicating that the thin film had clearly been melted and solidified.

実施例３．実施例２の８　ｉ、Ｎ、基板に低温のＣＶ−
Ｄで７００°０で８ｉを３０００λ堆積し８けを５０Ｋ
Ｖ。Example 3. Example 2 8 i, N, low temperature CV-
Deposit 3000λ of 8i at 700°0 in D and heat 8 pieces at 50K
V.

２８０ＫＶで夫ｋ　２　Ｘ　１０１’　／ｄ　、　３Ｘ
１　Ｇ”／ｃｄイオン注入した。この基板を３５０℃に
保ち、７ＷのＡｒレーザーを１００μｍφに絞シ１５信
／＄・Ｃの線速度で走査した。又同様に基板を３００℃
に保ち５ＫＶ、１．５ｍ人の電子ビームを１００１Ａφ
に絞り２０ｃＷ＠／ｓｅｅの線速度で走査した。これら
の場合もＴＦＳＭ観察により、基板にエツチングにより
作うれた鋭い端辺から結晶成長が固相で起っているのが
認められた。この為、３０μｍ×２０μｍの部分ではエ
ネルギービームが始に到来した側からの結晶粒成長が主
に認められた。この付近の結晶粒径は２〜ｌＯμｍに分
布していた。又ビームが通過し終る儒では結晶粒径は０
．５〜５μｍであった。この薄膜に形成した同上のＭ０
８トランジスタの電子μＦｍは熱アニールのそれと同様
の平均値と標準偏差を示した。この場合Ａｒレーザーを
ＩＯＷ、電子ビーム電流を２．２ｍＡに上昇せしめると
薄膜が溶融・固化したのが８ＷＭＫ：より關められた。At 280KV, 2 x 101'/d, 3X
1 G"/cd ions were implanted. This substrate was kept at 350°C, and a 7W Ar laser was focused to 100 μmφ and scanned at a linear velocity of 15 pulses/$・C. Similarly, the substrate was kept at 300°C.
Keep the electron beam at 5KV and 1.5m person at 1001Aφ.
Scanning was performed at a linear speed of 20 cW@/see. In these cases as well, TFSM observation revealed that crystal growth occurred in the solid phase from the sharp edges created by etching the substrate. Therefore, in the 30 μm×20 μm area, crystal grain growth was mainly observed from the side where the energy beam first arrived. The crystal grain size in this vicinity was distributed in the range of 2 to 10 μm. Also, the crystal grain size is 0 at the point where the beam finishes passing through.
．． It was 5 to 5 μm. The same M0 formed on this thin film
The electron μFm of the 8 transistors showed an average value and standard deviation similar to those of the thermal annealing. In this case, when the Ar laser was set to IOW and the electron beam current was increased to 2.2 mA, the thin film melted and solidified.

この際の結晶粒、μｒｘ等は前述の液相成長の結果と同
震度であった。すなわち声Ｆｍ〜３００　ｃｄ／　ｖ　
ｓｅｅ　８度でありながらその標準偏差は５５ｄ／ｖｓ
ｅｃというバラツキの大きいものであった。The crystal grains, μrx, etc. at this time had the same seismic intensity as the results of the liquid phase growth described above. That is, voice Fm~300 cd/v
see Although it is 8 degrees, its standard deviation is 55 d/vs
There was a large variation in ec.

以上のように本発明はキャリア易動度の大きい半導体薄
膜構造とその製造方法を提供するものと言える。As described above, it can be said that the present invention provides a semiconductor thin film structure with high carrier mobility and a method for manufacturing the same.

向側として８ｉ基板上に絶縁薄膜を形成する方法につい
て述べたが溶融石英板、サファイア板、更にこの上に堆
積した絶縁薄膜等であっても良い。Although the method for forming an insulating thin film on the 8i substrate has been described, it may also be a fused quartz plate, a sapphire plate, or an insulating thin film deposited thereon.

又Ｓｉを例として述べたがＧｅ又は化合物半導体でも良
い、後者の場合ではイオン注入として構成元素すべてを
行うことが望ましい。Further, although Si has been described as an example, Ge or a compound semiconductor may also be used. In the latter case, it is desirable to perform ion implantation of all the constituent elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　〜（ｇ）は本発明の実１１１！’ＩＬＪ
Ｄ断面図、第２図は突出ストライプパターンの斜視図、
第３図は突出網状パターンの斜視図、ｔｉｃ４図は突出
ストライプパターンではエネルギービームが先に到着し
た側から結晶粒成長が見られるととを示す概念図である
。 図に於いて、 １・・・・Ｓ１ウエハ　　　　２・・・・酸化膜３・・
・・レジスト　　　　　４・・・・　８蚤５・・・・ン
ース　　　　　　６・・・・　ドレイン７・・・・ゲー
ト酸化膜　　８・・・・ゲート電極代理人　弁理士　　
則　近　憲　佑　（ほか１名）第　　１　　図 第２図 第３図 第４図 ７２−Figures 1(a) to (g) show the fruits of the present invention 111! 'ILJ
D sectional view, FIG. 2 is a perspective view of the protruding stripe pattern,
FIG. 3 is a perspective view of the protruding net pattern, and FIG. 4 is a conceptual diagram showing that in the protruding stripe pattern, crystal grain growth is observed from the side where the energy beam arrives first. In the figure, 1...S1 wafer 2...Oxide film 3...
...Resist 4...8 Flea 5...Nose 6...Drain 7...Gate oxide film 8...Gate electrode agent Patent attorney
Kensuke Chika (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 4 72-

Claims (1)

【特許請求の範囲】 １）絶縁基板表面を、この上に堆積する半導体薄膜の厚
さと比べて小さい深さを有する周期的、非周期溝或は突
起構造に加工する工程、この上にアモルファス半導体薄
膜を堆積する工程、熱１ｆＪ１１１により固相成長せし
める工程により太き々結晶粒を形成する半導体薄膜の製
造方法。 ２）溝又は突起構造の長さ方向を９０°異なる二方向に
設定することを特徴とする特許 範囲第１項記載の半導体薄膜の製造方法。 ３）絶縁基板上に半導体薄膜を堆積後、半導体構成元素
をイオン注入することを特徴とする前記特許請求の範囲
第１項記載の半導体薄膜の製造方法。 ４）半導体薄膜を強い光強度の゛レーザー光、電子ビー
ム等のエネルギービームで照射し，同相成長せしめるこ
とを特徴とする前記特許請求の範囲第１項記載の半導体
薄膜の製造方法。[Claims] 1) Processing the surface of an insulating substrate into a periodic or non-periodic groove or protrusion structure having a depth smaller than the thickness of a semiconductor thin film deposited thereon; A method for manufacturing a semiconductor thin film in which thick crystal grains are formed by a step of depositing a thin film and a step of solid phase growth using heat 1fJ111. 2) The method for manufacturing a semiconductor thin film according to the patent scope 1, characterized in that the length directions of the groove or protrusion structure are set in two directions different by 90 degrees. 3) A method for manufacturing a semiconductor thin film according to claim 1, characterized in that after depositing the semiconductor thin film on an insulating substrate, ions of semiconductor constituent elements are implanted. 4) A method for manufacturing a semiconductor thin film according to claim 1, characterized in that the semiconductor thin film is irradiated with an energy beam such as a laser beam or an electron beam with high light intensity to cause in-phase growth.
JP56153743A 1981-09-30 1981-09-30 Manufacture of semiconductor thin film Pending JPS5856317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56153743A JPS5856317A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56153743A JPS5856317A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor thin film

Publications (1)

Publication Number Publication Date
JPS5856317A true JPS5856317A (en) 1983-04-04

Family

ID=15569133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56153743A Pending JPS5856317A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor thin film

Country Status (1)

Country Link
JP (1) JPS5856317A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5505816A (en) * 1993-12-16 1996-04-09 International Business Machines Corporation Etching of silicon dioxide selectively to silicon nitride and polysilicon
JP2004006728A (en) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
JP2007142167A (en) * 2005-11-18 2007-06-07 Hitachi Displays Ltd Display device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5505816A (en) * 1993-12-16 1996-04-09 International Business Machines Corporation Etching of silicon dioxide selectively to silicon nitride and polysilicon
JP2004006728A (en) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
JP2007142167A (en) * 2005-11-18 2007-06-07 Hitachi Displays Ltd Display device and its manufacturing method

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