JPS5856406A - Production of semiconductor film - Google Patents

Production of semiconductor film

Info

Publication number
JPS5856406A
JPS5856406A JP56155149A JP15514981A JPS5856406A JP S5856406 A JPS5856406 A JP S5856406A JP 56155149 A JP56155149 A JP 56155149A JP 15514981 A JP15514981 A JP 15514981A JP S5856406 A JPS5856406 A JP S5856406A
Authority
JP
Japan
Prior art keywords
film
semiconductor film
amorphous
substrate
crystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56155149A
Other languages
Japanese (ja)
Inventor
Kazumichi Omura
大村　八通
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56155149A priority Critical patent/JPS5856406A/en
Publication of JPS5856406A publication Critical patent/JPS5856406A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form a highly uniform semiconductor film allowing carriers to readily move on an insulating substrate by a method wherein a small piece of a thin film is formed at such temperatures that crystallization will not occur on the surface of an amorphous semiconductor film and a crystalline nucleus is produced by annealing so as to uniformly crystallize the amorphous semiconductor film by causing the film to grow in a solid phase. CONSTITUTION:An amorphous Si film 2 is formed on top of a Si monocrystalline substrate 1 where a thermo-oxidized film has been formed and small pieces of SiO2 films 3 are formed on top of the amorphous Si film in the form of a grit. If these small pieces are annealed at relatively low temperatures, a crystalline cleus 4 is produced on the periphery of each small piece of the SiO2 film. Crystalline particles grow with the crystalline nucleus 4 as the center according to the growth in a solid phase, so that a polycrystalline Si film 5 having uniform particles in diameter is obtainable over the whole surface of the wafer. Thus, highly uniform semiconductor films offering excellent element characteristics can be manufactured. Moreover, since annealing is conducted at temperatures that are unable to fuse the semiconductor film, this manufacturing method is useful when the elements have already been formed on the substrate integratedly or when three-dimensional IC's are formed.

Description

【発明の詳細な説明】 本発明は絶縁性基板上のすぐれた半導体膜、就中均一性
が良くキャリア易動度の高い半導体膜の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for producing an excellent semiconductor film on an insulating substrate, particularly a semiconductor film with good uniformity and high carrier mobility.

絶縁性基板上の半導体単結晶膜はＳＯＳ　（サファイア
上のシリコン）の例でも判るように次のような利点を有
する。すなわち■薄膜を島状に分離し、又は膜厚全体に
わたる銹電体分離により素子間の分離が容易且つ完全に
出来る。■拡散、イオン注入等で不純物を絶縁性基板界
面まで導入するときはｐ−ｎ接合の面積を著しく小さく
出来るため浮遊容量が小さく、従って高速動作が可能と
なる。■この薄膜上にＭＯＳインバータを形成するとき
は基板バイアス効果がないためスイッチング速度が大き
い。A semiconductor single crystal film on an insulating substrate has the following advantages, as can be seen from the example of SOS (silicon on sapphire). That is, (1) isolation between elements can be easily and completely achieved by separating the thin film into islands or by electrically separating the elements over the entire film thickness; (2) When impurities are introduced to the interface of an insulating substrate by diffusion, ion implantation, etc., the area of the pn junction can be significantly reduced, resulting in a small stray capacitance and therefore high-speed operation. (2) When a MOS inverter is formed on this thin film, the switching speed is high because there is no substrate bias effect.

ところで、　ＳＯＳは単結晶サファイアを使用するため
高価となるので、溶融石英板や、Ｓｉ基板を酸化して形
成したアモルファス５ｔｏ２膜やＳＮ基板上に堆積した
ＳＩＮ膜上に半導体膜を更に堆積したものを使用する試
みがある。これら５ｔｏｚやＳＩＮは単結晶でないので
、この上に半導体単結晶膜は成長出来ず多結晶膜が成長
するのみである。そのため最近レーザーや電子ビームを
細く絞って半導体膜上を線状に走査し、溶融固化を行わ
せることにより、その結晶粒径を増大せしめ得る方法が
発表されている。このような方法によシ数尾の結晶粒の
ものも得られ、このような薄膜上に形成したｎチャネル
ＭＯ８）ランジスタでは電界効果易動度の最大が４００
３／Ｇ、　ｍｅとバルク上のそれの半分近くにも達する
ものも得られている。By the way, SOS is expensive because it uses single crystal sapphire, so it is possible to use a fused silica plate, an amorphous 5to2 film formed by oxidizing a Si substrate, or a semiconductor film further deposited on an SIN film deposited on an SN substrate. There is an attempt to use . Since these 5toz and SIN are not single crystals, a semiconductor single crystal film cannot be grown thereon, and only a polycrystalline film can be grown thereon. Therefore, recently, a method has been announced in which the crystal grain size can be increased by narrowing a laser or electron beam to linearly scan the semiconductor film and melting and solidifying the semiconductor film. By this method, crystal grains with several grains can be obtained, and in an n-channel MO transistor formed on such a thin film, the maximum field-effect mobility is 400.
3/G, me, which is nearly half of that in bulk, has been obtained.

しかしながらこのような方法で得られた薄膜デバイスに
は次のような欠点が見られる。すなわち上述のＭＯＳ　
）ランジスタはチャネル幅Ｗ＝２００μｍ１チャネル長
Ｌ−ａｌｏｏａ＆、といった大面積の素子であるが、こ
れがＷ−１０朗ＩＬ−６μｍといった小面積のＭｌ）Ｂ
　）ランジスタの場−合、確かに易動度が４００　ｃｎ
ｓ２／ｖ、　ｓ・Ｃ程度のものがある一方で、１０５１
シマ、　ｓｅｅ程度しかない素子ヤ、ソース・ドレイン
間の残留リーク電流の多い素子が多数あることである。However, the thin film device obtained by this method has the following drawbacks. That is, the above-mentioned MOS
) A transistor is a large-area element with a channel width W = 200 μm and a channel length L-alooa&, but this is a small-area element such as W-10L-6 μm.
) In the case of transistors, the mobility is certainly 400 cn.
While there are s2/v, s・C, 1051
The problem is that there are a large number of devices that have only the appearance of stripes or see, and a large number of devices that have a large amount of residual leakage current between the source and drain.

このような素子をＳＥＭ等で調べてみると、それらは素
子製作前のウェハ上の凸凹部分に作られた場合や、レー
デ−ビームや電子ビームの走査帯のへ９に沿って存在す
る場合でろることが判った。このようなエネルギービー
ムの走査では溶融、固化を伴なうので結晶粒が始めの平
坦な堆積多結晶面から突出し、或は陥没し凸凹を生ずる
。又走査帯のヘリではエネルギー密度が弱く、重ね走査
を行なってもその時の走査帯のヘリに同様の効果を生じ
、結晶粒の液相成長が不十分であったシ、不均一のため
素子の特性が悪いものと考えられる。一方このようなエ
ネルギービームによる液相成長によらない場合の絶縁体
上の半導体膜を考えると、ＣＶＤ堆積したＳｌは数１０
Ｘ程度の微細結晶であるが、１０００℃以上に熱すると
多少の結晶粒成長が見られ数１００Ｘの粒径になる。し
かしこのような半導体膜にＭ９８Ｘ子を形成しても通常
の特性を示さず電子易動度も１ｃ！Ｒ２／マ０口。。と
小さい。When such devices are examined using a SEM, etc., they are found to be fabricated on uneven parts of the wafer before device fabrication, or along the edges of the radar beam or electron beam scanning band. It turns out that Since such energy beam scanning involves melting and solidification, crystal grains protrude from the initially flat deposited polycrystalline surface, or are depressed, resulting in unevenness. In addition, the energy density is weak at the edge of the scanning band, and even if overlapping scanning is performed, the same effect will occur at the edge of the scanning band at that time, and the liquid phase growth of crystal grains will be insufficient, and the non-uniformity will cause the device to deteriorate. It is considered to have poor characteristics. On the other hand, if we consider a semiconductor film on an insulator that does not rely on liquid phase growth using an energy beam, CVD-deposited Sl will be in the tens of thousands.
Although it is a fine crystal of about X size, when heated to 1000° C. or higher, some crystal grain growth is observed and the grain size becomes several 100X. However, even if M98X atoms are formed in such a semiconductor film, they do not exhibit normal characteristics and the electron mobility is only 1c! R2/Ma0 mouth. . And small.

本発明はこのような事情に鑑みてなされたもので、溶融
液相成長によらず、絶縁性基板上に均一性のすぐれたキ
ャリア易動度の大きい半導体膜を形成する方法を提供す
るものである。The present invention has been made in view of the above circumstances, and provides a method for forming a semiconductor film with excellent uniformity and high carrier mobility on an insulating substrate without using melt phase growth. be.

本発明は次のような知見に基いている。すなわち前述の
ＣＶＤ堆積したＳＮ膜は微細な多結晶であるが、これに
Ｓｔイオ／注入を行なうと、そのイオンドーズが比較的
高濃度であると完全なアモルファス状態となることが電
子線、Ｘ線回折で判る。又、絶縁性基板が室温程度であ
ると、真、空蒸着したＳ１膜も又、アモルファスとなっ
ている。このような試料を９００−１０００℃で熱処理
すると（至）堆積Ｓｌ膜の場合と同じく数１００Ｘの粒
径の多結晶となる。熱処理温度を下げると得られる結晶
粒径が大きくなる・同時にアモルファス層が全部多結晶
化する時間が長くなる。　Ｓｔの場合熱処理温度が６０
０℃以下になると数千又のアモルファス膜では数十時間
となる。この場合アモルファス層中に発生した結晶核か
ら樹枝状晶が発達して行き数十μｍの粒径のものが得ら
れることが判った。所がこのような結晶成長は核生成が
全く偶発的なものであシ、且つわずかの温度のゆらぎで
成長が止ったりする。The present invention is based on the following findings. In other words, the CVD-deposited SN film described above is a fine polycrystal, but when St ions are implanted into it, it becomes completely amorphous if the ion dose is relatively high. Determined by line diffraction. Further, when the insulating substrate is at about room temperature, the vacuum-deposited S1 film also becomes amorphous. When such a sample is heat-treated at 900-1000° C., it becomes polycrystalline with a grain size of several 100× as in the case of the deposited Sl film. Lowering the heat treatment temperature increases the resulting crystal grain size and at the same time increases the time it takes for the entire amorphous layer to become polycrystalline. In the case of St, the heat treatment temperature is 60
When the temperature drops below 0°C, it takes several tens of hours for an amorphous film with several thousand lines. In this case, it was found that dendrites develop from crystal nuclei generated in the amorphous layer, resulting in grains with a diameter of several tens of micrometers. However, in such crystal growth, nucleation is entirely accidental, and growth can be stopped by slight fluctuations in temperature.

そこで本発明では、絶縁性基板上のアモルファス半導体
膜表面にその結晶化がおこらない温度で所定ノ々ターン
の他の薄膜小片を形成し、アニールによりてその薄膜小
片の周辺から結晶核発生を起させてアモルファス半導体
膜を固相成長により均一性よく結晶化することを特徴と
している。Therefore, in the present invention, another thin film piece with a predetermined number of turns is formed on the surface of the amorphous semiconductor film on an insulating substrate at a temperature that does not cause crystallization, and crystal nuclei are generated from the periphery of the thin film piece by annealing. The method is characterized in that an amorphous semiconductor film can be crystallized with good uniformity by solid phase growth.

以下本発明の詳細な説明する。８１単結晶基板ｆ：１０
００℃、１６０分ドライ酸化して１０００Ｘの熱酸化膜
を形成した。この上に、１０−’Ｔｏｒｒ　　の真空で
基板を室温に保ってアモルファス−８１膜を３０００Ｘ
蒸着したーこの上にスパッターにより　５ｉＯｚ膜を１
０００１堆積し、光食側法によシ１０　ｔｈｍ間隔の格
子点に１μｍ角の５ｔｏｂ た。このＳ１ウエハ（４インチ直径）１に５５０　℃の
炉に入れＮ２ガスを流し５０時間アニールした。The present invention will be explained in detail below. 81 single crystal substrate f:10
Dry oxidation was performed at 00°C for 160 minutes to form a 1000X thermal oxide film. On top of this, an amorphous-81 film was deposited at 3000X while keeping the substrate at room temperature in a vacuum of 10-'Torr.
On top of this, a 5iOz film was deposited by sputtering.
0001 was deposited, and 5 pieces of 1 μm square were deposited on lattice points spaced at 10 thm intervals using the photo-eclipsed side method. This S1 wafer (4 inch diameter) 1 was placed in a 550° C. furnace and N2 gas was supplied thereto to anneal it for 50 hours.

これによシアモルファスＳＩＭはウェハ全面に亘ジ結晶
化した。Ｓｌ単結晶基板側からエッチして薄片を作シ透
過電子顕微鏡で観察した結果、表面の１μ角の５ｉｏｂ 生しており、このような結晶発生が１０μｍ間隔の格子
点から起るので得られた結晶粒はウェハ全面に亘シ３−
８μ情と均一であった。As a result, the shear amorphous SIM was di-crystallized over the entire surface of the wafer. A thin section was etched from the side of the Sl single crystal substrate and observed under a transmission electron microscope. As a result, 5 IOBs of 1 μm square were grown on the surface, and this was obtained because such crystal generation occurs from lattice points spaced at 10 μm intervals. The crystal grains spread over the entire wafer surface.
The results were uniform at 8 μm.

第１図および第２図は本実施例でのアモルファスＳｔ膜
の結晶化の様子を模式的に示している。FIGS. 1 and 2 schematically show the state of crystallization of the amorphous St film in this example.

即ち第１図に示すように、熱酸化膜を形成したｓｉ単結
晶基板１にアモルファス８１！ｘ２を形成し、その上に
５ｉｏｂ て比較的低温でアニールすると、まず各８１０２膜小片
３０周辺に結晶核４が発生する。そしてこの結晶核４′
ｆｃ中心として固相成長により結晶粒が成長し、第２図
に示すようなウエノ）全面にわたって均一な粒径の多結
晶ｓｉ膜５が得られる。That is, as shown in FIG. 1, an amorphous 81! When x2 is formed and 5 iob is annealed thereon at a relatively low temperature, crystal nuclei 4 are first generated around each 8102 film piece 30. And this crystal nucleus 4'
Crystal grains grow at the fc center by solid phase growth, and a polycrystalline Si film 5 having a uniform grain size over the entire surface as shown in FIG. 2 is obtained.

ちなみに、　　５ｔｃ）２膜小片を設けず、同様の熱処
埠を行った４インチクエバを観察すると、ウェハを搭載
する石英メートに立てた部分で結晶化が進んでいたが、
上部では未だアモルファス膜が残っていた。また、結晶
核発生位置はランダムに分布しており、結晶粒径も１μ
ｍ以下から１５−位まで分布していた。By the way, when we observed a 4-inch cube that had been subjected to the same heat treatment without the 5tc) 2 film piece, we found that crystallization had progressed in the area where the wafer was mounted on the quartz mate.
An amorphous film still remained at the top. In addition, the crystal nucleus generation positions are randomly distributed, and the crystal grain size is 1 μm.
It was distributed from below m to 15-position.

以上のような現象は、レーデや電子線によるアニールで
も見られた。すなわち上記実施例と同様のウェハに７０
μｍ程度に集束したＡｒレーデや電子ビームを５Ｗ程度
、１０−２０ｃ１１ｖ／ｓｅｅの速度で走査照射した。The above phenomenon was also observed in LED and electron beam annealing. In other words, 70
Scanning irradiation was performed with an Ar radar or electron beam focused on the order of μm at a rate of about 5 W and 10-20 c11v/see.

　８１０２膜小片ノ譬ターンのない場合にはウェハ全面
を１０回走査するとウェハ中心に結晶核が多く発生して
おり、周辺にはアモルファス部が残っていた。５ｉｏｂ
ーンを形成したウェハに上記のようなビームで走査した
場合には、やはＤ　ＳｌＯｚｇ小片の周辺からの結晶核
発生がウェハ全体にわたって起っており、結晶粒径もウ
ェハ全体にわたって均一で、２−７μｍであった。これ
らのレーザー、電子ビームはこの程度の出方、走査速度
ではＳＩ基板に与える効果は全く加熱効果でありしかも
固相成長が進行するが溶融には至らない程度のものであ
るので同様の結果を示したものであろう。When the entire surface of the wafer was scanned 10 times in the case of the 8102 film without any turns, many crystal nuclei were generated at the center of the wafer, and amorphous portions remained at the periphery. 5 iob
When scanning a wafer with a grain formed thereon with the beam as described above, crystal nucleation occurs from the periphery of the D SlOzg pieces over the entire wafer, and the crystal grain size is uniform over the entire wafer. It was 2-7 μm. With these laser beams and electron beams at this level of output and scanning speed, the effect on the SI substrate is purely a heating effect, and although solid phase growth progresses, it does not lead to melting, so similar results could be obtained. It must have been shown.

次に別の実施例を説明する。ｓ１単結晶基板に熱酸化膜
を１００ＯＸ上記実施例と同様に形成し、ＣＶＴ）で多
結晶５ｌＦＩＸを４０００芙堆積した。そして３００ｋ
Ｖ　、　１５０ｋＶテＳｉを夫ｋ　Ｉ　Ｘ　１０’シ３
２イオン注入した。これにより多結晶ｓ１膜が全くアモ
ルファスとなったことが、層剥離と反射電子線回折で判
った。その後上記実施例と同じようにスノ平、夕で１０
０ＯＸの５ｉｏ２膜を被着、光食刻法で１＃Ｌ角の８１
０２膜小片を２０篇間隔の格子点に残して配置した。こ
のようなパターンを被着する場合最高２００℃程度温度
上昇があるのみである。この４インチ径つェへｔ−５５
０℃の炉中でＮ２ガスを流して７５時間熱処理した。Next, another embodiment will be described. A thermal oxide film of 100 OX was formed on the s1 single crystal substrate in the same manner as in the above embodiment, and 4000 OX of polycrystalline 5lFIX was deposited using CVT. and 300k
V, 150kV te Si Huk I X 10'Si 3
2 ions were implanted. As a result, the polycrystalline s1 film became completely amorphous, as revealed by layer peeling and reflection electron diffraction. After that, same as the above example, Sunodaira, 10 in the evening.
Deposited 0OX 5io2 film, photoetched 1#L square 81
02 membrane pieces were left at grid points at intervals of 20 pieces. When depositing such a pattern, there is only a temperature rise of about 200° C. at most. This 4 inch diameter thread T-55
Heat treatment was performed for 75 hours in a furnace at 0° C. by flowing N2 gas.

透過電子顕微鏡で観察した結果、３３−９ｔの粒径の結
晶粒が得られた。一方５ｔｏ２膜小片バトンを被着しな
いウェハでは全面結晶化はしていたが０．５篇から１５
μｍの粒径で不均一であった。得られた多結晶ｓ１膜に
チャネル幅３０尾、チャネル長２０篇のｎチャネルＭｏ
ｓトランジスタ　　□を形成してその特性を測定した。As a result of observation with a transmission electron microscope, crystal grains with a grain size of 33-9t were obtained. On the other hand, wafers that were not covered with the 5to2 film small piece baton were crystallized on the entire surface, but from 0.5 to 15
The particles were non-uniform with a particle size of μm. The resulting polycrystalline s1 film was coated with n-channel Mo with a channel width of 30 strands and a channel length of 20 strands.
An s transistor □ was formed and its characteristics were measured.

本実施例の場合、電界効果易動度の最大μｍの平均は３
００ａｖｖ、　！＋１！ｌｅ、標準偏差は３０ｃＨ？／
マ・−・Ｃであったが、　５ｉｏｂ片／辛ターンを被着
しないウェハではμｍの平均はｚ９ｏａ５＾、ｓｅｅと
余）変らないものの、標準偏差が６０ｃｍ２／マ、ｓ＠
ｅ４あシネ均一であった。In the case of this example, the average maximum field effect mobility is 3 μm.
00avv,! +1! le, standard deviation is 30cH? /
However, for wafers that do not have 5iob pieces/hard turns attached, the average μm is z9oa5^, see and other), but the standard deviation is 60cm2/ma,s@
The e4 film was uniform.

以上のように本発明は、均一性がよく、すぐれた素子特
性を示す半導体膜を製造することができる。また、アニ
ールは半導体膜を溶融しない＠度で行うから、基板が既
に素子が集積形成されたものである場合、つまり３次元
ＩＣを形成する場合に有用である。As described above, the present invention can produce a semiconductor film with good uniformity and excellent device characteristics. Furthermore, since annealing is performed at a temperature that does not melt the semiconductor film, it is useful when the substrate already has elements integrated therein, that is, when forming a three-dimensional IC.

なお、アモルファス膜上の薄膜小片を周期的に配置した
例を示したが、チップ内で異なる周期の配列や非周期的
配列で結晶粒発生を制御してもよい。また基板、半導体
膜、薄膜小片の材料や、多結６裟をイオン注入でアモル
ファス化する際の元′Ｊ＃１どは必要にＬじて任意に選
択できる。Although an example has been shown in which the thin film pieces on the amorphous film are arranged periodically, the generation of crystal grains may be controlled by arranging the thin film pieces on the amorphous film in a different periodic arrangement or in an aperiodic arrangement within the chip. Further, the materials of the substrate, the semiconductor film, the thin film pieces, and the elements used to make the polycrystalline material amorphous by ion implantation can be arbitrarily selected as required.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例においてアモルファスＳＮ膜
に結晶核が発生する様子を示す断面図、第２図は同じく
アモルファスＳ１膜が多結晶化した様子を示す断面図で
ある。 １・・・熱酸化膜でおおわれ九Ｓｔ単結晶基板、２・・
・アモルファスＳ１膜、３・−８ｉ０２膜小片、４・・
・結晶核、５・・・多結晶Ｓｔ膜。 出願人代理人　　弁理士　鈴　江　武　彦第１図FIG. 1 is a cross-sectional view showing how crystal nuclei are generated in an amorphous SN film in an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing how an amorphous S1 film becomes polycrystalline. 1... Nine St single crystal substrate covered with thermal oxide film, 2...
・Amorphous S1 film, 3・-8i02 film piece, 4...
- Crystal nucleus, 5... polycrystalline St film. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (4)

【特許請求の範囲】[Claims] （１）絶縁性基板上にアモルファス半導体膜を堆積する
工程、このアモルファス半導体膜表面にその結晶化が起
らない温度で他の薄膜小片を所定パターンで形成する工
程、アニールによりこの薄膜小片の周辺から前記アモル
ファス半導体膜に結晶核を発生させ固相成長させる工程
を備えたことを％像とする半導体膜の製造方法。(1) A process of depositing an amorphous semiconductor film on an insulating substrate, a process of forming other thin film pieces in a predetermined pattern on the surface of this amorphous semiconductor film at a temperature that does not cause crystallization, and annealing to form the thin film pieces around the thin film pieces. A method for manufacturing a semiconductor film, comprising the step of generating crystal nuclei in the amorphous semiconductor film and performing solid phase growth. （２）　　アモルファス半導体膜は、ＣｖＤによシ堆積
した多結晶膜を同−半導体元素或は他の元素でイオン注
入によりアモルファス化したもの、または室温近傍で真
空蒸着により形成したものである特許請求の範囲第１項
記載の半導体膜の製造方法。(2) A patent claim in which the amorphous semiconductor film is a polycrystalline film deposited by CvD and made amorphous by ion implantation with the same semiconductor element or another element, or formed by vacuum evaporation near room temperature. A method for manufacturing a semiconductor film according to item 1. （３）薄膜小片４、周期的Ｉリーンで形成される特許請
求の範囲第１項記載の半導体膜の製造方法。(3) The method for manufacturing a semiconductor film according to claim 1, wherein the thin film pieces 4 are formed by periodic I-leaning. （４）絶縁性基板は、単結晶半導体基板の表面を絶縁膜
でおおったものである特許請求の範囲第１項記載の半導
体膜の製造方法。(4) The method for manufacturing a semiconductor film according to claim 1, wherein the insulating substrate is a single crystal semiconductor substrate whose surface is covered with an insulating film.
JP56155149A 1981-09-30 1981-09-30 Production of semiconductor film Pending JPS5856406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56155149A JPS5856406A (en) 1981-09-30 1981-09-30 Production of semiconductor film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56155149A JPS5856406A (en) 1981-09-30 1981-09-30 Production of semiconductor film

Publications (1)

Publication Number Publication Date
JPS5856406A true JPS5856406A (en) 1983-04-04

Family

ID=15599601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56155149A Pending JPS5856406A (en) 1981-09-30 1981-09-30 Production of semiconductor film

Country Status (1)

Country Link
JP (1) JPS5856406A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008206A (en) * 1986-07-11 1991-04-16 Canon Kabushiki Kaisha Method for making a photoelectric conversion device using an amorphous nucleation site
US5013670A (en) * 1986-09-18 1991-05-07 Canon Kabushiki Kaisha Photoelectric converter
US5207863A (en) * 1990-04-06 1993-05-04 Canon Kabushiki Kaisha Crystal growth method and crystalline article obtained by said method
US5290712A (en) * 1989-03-31 1994-03-01 Canon Kabushiki Kaisha Process for forming crystalline semiconductor film
US5318661A (en) * 1990-08-08 1994-06-07 Canon Kabushiki Kaisha Process for growing crystalline thin film
US5422302A (en) * 1986-06-30 1995-06-06 Canon Kk Method for producing a three-dimensional semiconductor device
US5457058A (en) * 1989-10-09 1995-10-10 Canon Kabushiki Kaisha Crystal growth method
US5495824A (en) * 1990-04-10 1996-03-05 Canon Kabushiki Kaisha Method for forming semiconductor thin film

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422302A (en) * 1986-06-30 1995-06-06 Canon Kk Method for producing a three-dimensional semiconductor device
US5008206A (en) * 1986-07-11 1991-04-16 Canon Kabushiki Kaisha Method for making a photoelectric conversion device using an amorphous nucleation site
US5013670A (en) * 1986-09-18 1991-05-07 Canon Kabushiki Kaisha Photoelectric converter
US5290712A (en) * 1989-03-31 1994-03-01 Canon Kabushiki Kaisha Process for forming crystalline semiconductor film
US5457058A (en) * 1989-10-09 1995-10-10 Canon Kabushiki Kaisha Crystal growth method
US5207863A (en) * 1990-04-06 1993-05-04 Canon Kabushiki Kaisha Crystal growth method and crystalline article obtained by said method
US5495824A (en) * 1990-04-10 1996-03-05 Canon Kabushiki Kaisha Method for forming semiconductor thin film
US5318661A (en) * 1990-08-08 1994-06-07 Canon Kabushiki Kaisha Process for growing crystalline thin film

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