JPS5863173A - Polycrystalline thin film transistor - Google Patents

Abstract

PURPOSE:To obtain an MIS FET having a high carrier mobility by forming a polycrystalline semiconductor layer of columnar structure on non-crystalline or polycrystalline substrate and disposing electrodes to produce an electric field parallel to the axis of the columnar structure, thereby moving the carrier in a direction parallel to the axis of the column with good crystallinity and less defects. CONSTITUTION:5-layers are deposited in vacuum on an amorphous insulating substrate 15 made of like glass. Molybdenum is deposited as a source electrode 8, silicon is then deposited as a high density impurity-added semiconductor layer 9 in vacuum by an electron gun while evaporating N type impurity in a crucible, and only silicon is subsequently grown in polycrystal as no-addition semiconductor active layer 10. Again, an impurity addition is restarted, and a high density impurity-added semiconductor layer 11 is grown in the same method as the layer 9. Further, molybdenum is deposited in vacuum as the drain electrode 12 in the same manner as the source electrode 8. Then, as shown in Fig. b, it is etched by dry etching vertically to the substrate along the polycrystallie column, and an insulating layer such as nitrided silicon is formed by a plasma CVD as shown in Fig. c. A gate electrode 14 is eventually deposited as shown in Fig. d, thereby forming a polycrystalline MIS FET.

Description

[Detailed Description of the Invention] The present invention provides a metal/insulator/semiconductor field effect transistor (hereinafter abbreviated as MIS FET) using a polycrystalline semiconductor thin film.
Regarding.

Conventionally, MIS FETs have been manufactured by using a single crystal semiconductor substrate such as 81 and implanting impurities into the substrate or onto the surface thereof by methods such as diffusion and ion implantation.

Therefore, it is not possible to freely select substrates such as glass,
An expensive single crystal semiconductor substrate was required.

Therefore, discharge decomposition (Glov) is performed on an amorphous or polycrystalline substrate.
Discharge) or polycrystalline MIS FE using amorphous and polycrystalline semiconductor thin films made by vacuum evaporation.
The structure of this polycrystalline MIS FET is shown in Figure 1. In the figure, 1 is the source electrode, 2 is the gate electrode,
6 is a drain electrode, 4 is an insulating layer, 5 is a female layer, 6 is an amorphous or polycrystalline semiconductor layer, and 7 is an amorphous or polycrystalline substrate. Here, FIG. 1(a) is the source.

(b) t (a) shows a Cochraner type in which the drain and gate electrodes are placed on the thin film surface, and (a) shows a configuration in which the source and drain electrodes are placed on the thin film surface and the gate vL pole is placed on the substrate surface, or vice versa. It is a stagger type. These polycrystalline MIS Fli:T can be made using amorphous or polycrystalline substrates, but due to grain boundary scattering due to polycrystalline grain boundaries in the semiconductor, carrier mobility is lower than that of single-crystalline MIS FETs. The disadvantage is that it is very low. For example, those using polycrystalline silicon have carrier mobility of 1 to 10.
(cJ/V-eea) 9 degrees, and one using amorphous silicon operates only at a carrier mobility of about 0.1 (cIa/V-sθC).

An object of the present invention is to provide a MIS Fli:T structure that can be fabricated on an amorphous or polycrystalline substrate and has high carrier mobility.

Therefore, in the present invention, a polycrystalline semiconductor layer with a columnar structure is formed on an amorphous or polycrystalline substrate, and electrodes are arranged so as to generate an electric field parallel to the columnar axis of the columnar structure.
This is a polycrystalline MIS FET that achieves the above objective by moving carriers in a direction parallel to the column axis with fewer defects.

The present invention will be explained below using the drawings. Figure 2 is a photograph of a scanning electron microscope image of a cross section of a polycrystalline silicon thin film formed by vacuum deposition on a polycrystalline substrate, and the magnification is as shown in Figure 2 (
a) is 3x10' times, (b) is 5x10' times. In this way, a polycrystalline semiconductor having a columnar diameter of several hundred angstroms and a uniform columnar structure can be grown from the substrate surface to a thickness of about 1 micrometer. Also here, the crystal <
The <110> or <100> direction is perpendicular to the substrate surface. The present invention moves the carrier parallel to the column axis of this columnar structure.

FIG. 3 shows an embodiment of the present invention along its manufacturing process. Here, 8 is a source electrode, 9111 is a heavily doped layer, 10 is a semiconductor active layer, 12 is a drain electrode, 13 is an insulating layer, 14 is a gate electrode, and 15 is a substrate. Figure 6 (, 11 shows the polycrystalline MIS FET of the present invention. This polycrystalline MIS FET has a carrier mobility of 40
~60 (crJ/V·sea), and operates faster than conventional polycrystalline MIS FETs.

Fig. 6 shows an example of a specific manufacturing method.
As shown in a), five layers are vacuum-deposited on an amorphous insulating substrate 15 such as glass. First, molybdenum was used as the source electrode 8.
．． 3. Next, the substrate temperature is kept below the substrate softening temperature, and the source '
#In order to obtain ohmic contact between the L pole 8 and the semiconductor active layer 10, silicon was vacuum-deposited using an electron gun while N-type impurities (phosphorus, arsenic, and antimony) were evaporated using a phosphor.
The i-crystal is grown to a thickness of 0 angstroms. Subsequently, as an additive-free semiconductor active layer 10, the addition of impurities is interrupted and only silicon is grown as a polycrystal to a thickness of 1.0 m4. The impurity addition is restarted again, and the highly doped semiconductor layer 11 is grown to a thickness of 200 angstroms in the same manner as the semiconductor layer 9.

Furthermore, similarly to the source electrode 8, a molybdenum film of 0.2 micrometers is vacuum-covered as a drain electrode 12. As shown in FIG. 3(b), an insulating layer of silicon nitride or the like is formed on the 5M metal and semiconductor layer as shown in FIG. 3(c).

Finally, the gate electrode 14 shown in FIG. 6(d) is
A polycrystalline MIS FET is formed by carbon evaporation.

As explained above, the present invention is a MIS FET that can be manufactured at low cost and operates at high speed.

[Brief explanation of the drawing]

Figure 1 (a), (b) (Q) shows conventional polycrystalline MIS F
A cross-sectional view showing the structure of ET, FIG.
a) (b) (cl) (d) is a cross-sectional view explaining an example of the present invention along the manufacturing process. In the figure, 1.8 is a source electrode, 2 and 14 are gate electrodes, and 3
, 12 is a drain electrode, 4.13 is an insulating layer, 5 is one layer,
6 is an amorphous or polycrystalline semiconductor layer, 7.15 is an amorphous or polycrystalline substrate, 9.11i is a high concentration impurity doped layer, 10
is a polycrystalline semiconductor active layer. Applicant: Canon Corporation (b) tμm α

Claims (1)

[Claims] A metal fist characterized by forming a polycrystalline semiconductor layer with a columnar structure on an amorphous or polycrystalline substrate, generating an electric field parallel to the columnar axis of the columnar structure, and moving a current carrier parallel to the columnar axis. Insulator/semiconductor field effect transistor.