JPS6043814A - Manufacture of semiconductor crystalline film - Google Patents
Manufacture of semiconductor crystalline filmInfo
- Publication number
- JPS6043814A JPS6043814A JP58151517A JP15151783A JPS6043814A JP S6043814 A JPS6043814 A JP S6043814A JP 58151517 A JP58151517 A JP 58151517A JP 15151783 A JP15151783 A JP 15151783A JP S6043814 A JPS6043814 A JP S6043814A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio2
- single crystal
- semiconductor
- electron beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の属する技術分野]
本発明は、絶縁性基板上にビームアニール法を用いて半
導体結晶薄膜を製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor crystal thin film on an insulating substrate using a beam annealing method.
[従来技術とその問題点コ
従来、例えば絶縁性基板上の半導体薄膜は5OS(サフ
ァイア上のシリコン)にみられるようにバルク半導体に
比べ、利点を有することが知られている。すなわち、■
島状に切断あるいは誘電体分離をするとき、素子間分離
が容易かつ確実に出来る。■p−n接合面積を小さくす
るととにより浮遊容量を小さく出来る等である。[Prior Art and Its Problems] Conventionally, it has been known that semiconductor thin films on insulating substrates, for example, have advantages over bulk semiconductors, as seen in 5OS (silicon on sapphire). In other words,■
When cutting into islands or performing dielectric isolation, isolation between elements can be easily and reliably achieved. (2) By reducing the pn junction area, stray capacitance can be reduced.
SO8は単結晶サファイアを使用するため高価となるの
で、溶融水晶板や、si大基板酸化17て形成した非晶
質SiO2やSi上に堆積した非晶質S ioz膜ある
いは非晶質8iN膜上に半導体膜を更に堆積したものを
使用する方法がある。これら5i02やSiNは単結晶
膜でないためその上には多結晶膜が成長する。この多結
晶膜の粒径は数百x程度で、この上にMOS)ランジス
タを形成してもそのキャリア移動度はバルクSi上のM
OB)ランジスタの数十分の一程度である。近年、レー
ザや電子ビームを細く絞って、半導体薄膜上を錦秋に走
査し溶融、固化を行わせることにより結晶粒径を増大さ
せる方法が試みられている。このような方法によって従
来の粒径の百倍にも相当する数μmの結晶粒が得られ、
そのため、その上に作ったデバイスの特性も向上する。SO8 is expensive because it uses single-crystal sapphire, so it is expensive to use on a fused quartz plate, amorphous SiO2 formed by oxidizing a large Si substrate, an amorphous SiOz film deposited on Si, or an amorphous 8iN film. There is a method in which a semiconductor film is further deposited. Since these 5i02 and SiN are not single crystal films, a polycrystalline film is grown thereon. The grain size of this polycrystalline film is about several hundred x, and even if a MOS transistor is formed on it, its carrier mobility is
OB) It is about one tenth of that of a transistor. In recent years, attempts have been made to increase the crystal grain size by focusing a narrow laser or electron beam and scanning the semiconductor thin film in a pattern to melt and solidify the semiconductor thin film. With this method, crystal grains of several μm, which is 100 times the conventional grain size, can be obtained.
Therefore, the characteristics of devices made on top of it also improve.
しかしながらこのような方法て得られたデバ・イスには
次のような欠点がみられる。すなわちMOSトランジス
タのチャネル長6μm、チャネル@】2μmといった小
面積のものについてキャリア移動度を測定してみると、
400d/ v−see程度のものがある反面、数十c
l/v−sec Lかない素子や、ソースドレーン間の
残留リーク電流の多い素子が多数あることである。これ
らの原因を解析したところ次のような問題点があること
がわかった。すなわちレーザビームや電子ビームのエネ
ルギー分布がガウス分布をしているためビームを走査し
た際、ビームのふちから中央へ向かって溶融、固化を引
き起す。それ故、結晶粒の成長がビームのふちから中央
に細かく伸びていく。このような場合、結晶粒径はある
程度まで大きくなるが、素子を形成すべき領域をすべて
単結晶化するまでには至らず、そのなかに結晶粒界が存
在することによって前述のように素子特性の劣化及び不
均一性をもたらしていた。However, the device obtained by this method has the following drawbacks. In other words, when measuring the carrier mobility of a MOS transistor with a small area such as a channel length of 6 μm and a channel of 2 μm, we find that
Some are about 400d/v-see, while others are about tens of c.
There are many devices with low l/v-sec L and devices with a large amount of residual leakage current between source and drain. When these causes were analyzed, the following problems were found. In other words, since the energy distribution of laser beams and electron beams has a Gaussian distribution, when the beam is scanned, it causes melting and solidification from the edges of the beam toward the center. Therefore, crystal grains grow finely from the edge of the beam to the center. In such a case, the crystal grain size increases to a certain extent, but it does not reach the point where all the regions in which the device is to be formed are made into single crystals, and the presence of crystal grain boundaries within the region deteriorates the device characteristics as described above. This resulted in deterioration and non-uniformity.
[発明の目的コ
この発明は上記の事情にムみてなされたもので電子ビー
ム照射による半導体薄膜の溶融とその後の固化の際ビー
ムの端部がらの核成長を抑制することによ多結晶性の優
れた半導体薄膜を得る方法を提供することを目的として
いる。[Purpose of the Invention] This invention was made in view of the above-mentioned circumstances, and it is possible to melt a semiconductor thin film by electron beam irradiation and suppress the growth of nuclei from the edge of the beam during solidification, thereby making it possible to form polycrystalline polycrystalline films. The purpose is to provide a method for obtaining excellent semiconductor thin films.
[発明の概要]
本発明では絶縁基板上の半導体膜に絶縁膜0を被着し、
その所定島状個所外の絶縁層の一部ないしは全部を除去
し、半導体膜における素子形成個所を中心とした領域上
の絶縁膜の厚さを、その周1711の領域のそれよシも
厚くした後、電子ビームを照射することによシ半導体膜
を再結晶化せしめる。[Summary of the invention] In the present invention, an insulating film 0 is deposited on a semiconductor film on an insulating substrate,
Part or all of the insulating layer outside of the predetermined island-shaped area was removed, and the thickness of the insulating film on the area of the semiconductor film centered on the element formation area was increased even further than that of the area 1711 around the area. After that, the semiconductor film is recrystallized by irradiating it with an electron beam.
[発明の効果]
本発明によれば、半導体薄膜に電子ビームを照射した際
、半導体薄膜上の厚い絶縁膜がおおわれている島状部分
へ投入されるエネルギーは薄い絶縁膜におおわれている
部分よシも少なくなシ、そのだめ溶融した後の固化段階
において、周囲部分よりも固化進行がはやく始まる。従
って、結晶成長は厚い絶縁膜がおおわれている島状部分
からその周囲に向かって結晶粒界がはいらないように進
むことになシ、その部分に作った素子の特性が均一でか
つすぐれたものとなる。[Effects of the Invention] According to the present invention, when a semiconductor thin film is irradiated with an electron beam, the energy input to the island-shaped portion of the semiconductor thin film covered with a thick insulating film is greater than that of the part covered with a thin insulating film. Since there is less oxidation, the solidification process starts faster than the surrounding area in the solidification stage after melting. Therefore, crystal growth must proceed from the island-like area covered with a thick insulating film to its surroundings without creating grain boundaries, and the characteristics of the device fabricated in that area will be uniform and excellent. becomes.
[発明の実施例]
第1図(a)〜(d)を参照して本発明の詳細な説明す
る。まず、(001’)単結晶Si基板11に1μmノ
5iOz膜を形成する(第1図(a))。[Embodiments of the Invention] The present invention will be described in detail with reference to FIGS. 1(a) to (d). First, a 1 μm thick 5 iOz film is formed on a (001') single crystal Si substrate 11 (FIG. 1(a)).
次に、その上に多結晶Si膜12を0.6 ttm 、
S i02膜13を0.3μm 111次被着しだ後
(第1図(+)) ) 、5i02膜13をリングラフ
ィ技術によシ島状に凸部15を作る。この時、凸部以外
の”02JPS B o、1μmまでエツチングする(
第1図(C))。このようにして作られた試作に対し、
CW電子ビームを、ビーム径150μmに絞り、加速エ
ネルギー7eV、ビーム電流2.5 m A 、ステッ
プ巾10μmで走査させ、アニールを行った。アニール
後のSi膜13の結晶性を透過電子顕微鏡で評価したと
ころ、5i02膜凸部15の下においては、はとんど欠
陥を含まない単結晶になっていることがわかった。この
単結晶領域内に、600Xのゲート酸化膜17を介して
、多結晶シリコンゲート電極18を形成し、不純物をド
ープしてソース15、ドレーン19を形成、チャネル長
4μnl、チャネル巾8μmのnチャネルトランジスタ
を作った(第1図(d) ) o実効キャリア移動度を
測定したところ800cffl/ v−seeであり、
バルクStを用いた場合とほぼ同等であることが確認さ
れた。また枚数の同様な領域KMO8)ランジスタを形
成した時の’I?性の均一性も優れたものであった。さ
らに、3i基板11に素子が存在する場合においても、
上記と同様すぐれた特性をもつデバイスをS i Jl
p4に形成することができ、積層デバイスを製作する方
法としても十分なものであることがわかった。Next, a polycrystalline Si film 12 with a thickness of 0.6 ttm is placed on top of the polycrystalline Si film 12.
After the SiO2 film 13 of 0.3 μm is deposited for the first time (FIG. 1 (+))), island-shaped convex portions 15 are formed on the 5IO2 film 13 by phosphorography. At this time, the areas other than the convex portions are etched to a depth of 1 μm (
Figure 1 (C)). For the prototype made in this way,
Annealing was performed by focusing a CW electron beam to a beam diameter of 150 μm and scanning with an acceleration energy of 7 eV, a beam current of 2.5 mA, and a step width of 10 μm. When the crystallinity of the Si film 13 after annealing was evaluated using a transmission electron microscope, it was found that under the 5i02 film convex portion 15, it was a single crystal containing almost no defects. In this single crystal region, a polycrystalline silicon gate electrode 18 is formed through a 600X gate oxide film 17, and an impurity is doped to form a source 15 and a drain 19. An n channel with a channel length of 4 μnl and a channel width of 8 μm. A transistor was made (Figure 1(d)). The effective carrier mobility was measured and was 800 cffl/v-see.
It was confirmed that the results were almost the same as those using bulk St. Also, 'I?' when forming similar number of area KMO8) transistors? The uniformity of the properties was also excellent. Furthermore, even when elements are present on the 3i substrate 11,
A device with the same excellent characteristics as above is S i Jl
It was found that the method can be formed to a p4 size and is sufficient as a method for manufacturing a laminated device.
上記の実施例において、薄膜にはSlを用いたがGe
、GaAsなどでもよいこと、また、下地基板絶縁膜の
材料及び形成方法によってその効果が減するものでない
ことは明きらかであシ、また、それぞれの膜厚、絶R膜
凸部の島の形状及び大きさもこれに限られないことはも
ちろんである0In the above example, Sl was used for the thin film, but Ge
, GaAs, etc., and it is clear that the effect is not diminished depending on the material and formation method of the underlying substrate insulating film. Of course, the shape and size are not limited to these.
第1図(a)〜(d)は本発明の一実施例を説明する工
程断面図である。
11・・・単結晶3i基板、 12・・・8 i0z膜
、B・・・多結晶SIs 14・・・S iOz膜、1
5・・・凸部、 16・・・ソース、17・・・ゲート
酸化筒、18・・・ゲート電極、19 ・ドレーン。
(7317)弁理士側近か佑
(ほか1名)
第 1 図FIGS. 1(a) to 1(d) are process sectional views illustrating an embodiment of the present invention. 11...Single crystal 3i substrate, 12...8 i0z film, B...polycrystalline SIs 14...S iOz film, 1
5... Convex portion, 16... Source, 17... Gate oxide tube, 18... Gate electrode, 19 - Drain. (7317) Kasuke, close to patent attorney (and 1 other person) Figure 1
Claims (1)
上に絶縁膜を被着する工程とを含み、所望島状領域外の
前記絶縁膜の一部乃至は全部を除去した後、該基板上か
ら電子ビームを照射することを特徴とする半導体結晶薄
膜の製造方法。The method includes a step of depositing a semiconductor film on an insulating substrate, and a step of depositing an insulating film on the semiconductor film, and after removing part or all of the insulating film outside the desired island-shaped region, A method for producing a semiconductor crystal thin film, which comprises irradiating the substrate with an electron beam.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58151517A JPS6043814A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor crystalline film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58151517A JPS6043814A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor crystalline film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6043814A true JPS6043814A (en) | 1985-03-08 |
Family
ID=15520235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58151517A Pending JPS6043814A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor crystalline film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6043814A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63142810A (en) * | 1986-12-05 | 1988-06-15 | Matsushita Electronics Corp | Manufacture of semiconductor device |
US6582777B1 (en) | 2000-02-17 | 2003-06-24 | Applied Materials Inc. | Electron beam modification of CVD deposited low dielectric constant materials |
US6652922B1 (en) * | 1995-06-15 | 2003-11-25 | Alliedsignal Inc. | Electron-beam processed films for microelectronics structures |
-
1983
- 1983-08-22 JP JP58151517A patent/JPS6043814A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63142810A (en) * | 1986-12-05 | 1988-06-15 | Matsushita Electronics Corp | Manufacture of semiconductor device |
US6652922B1 (en) * | 1995-06-15 | 2003-11-25 | Alliedsignal Inc. | Electron-beam processed films for microelectronics structures |
US6582777B1 (en) | 2000-02-17 | 2003-06-24 | Applied Materials Inc. | Electron beam modification of CVD deposited low dielectric constant materials |
US7309514B2 (en) | 2000-02-17 | 2007-12-18 | Applied Materials, Inc. | Electron beam modification of CVD deposited films, forming low dielectric constant materials |
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