JPS58501485A - 半導体基板の領域間に電気接触部を形成する方法 - Google Patents

半導体基板の領域間に電気接触部を形成する方法

Info

Publication number
JPS58501485A
JPS58501485A JP57502848A JP50284882A JPS58501485A JP S58501485 A JPS58501485 A JP S58501485A JP 57502848 A JP57502848 A JP 57502848A JP 50284882 A JP50284882 A JP 50284882A JP S58501485 A JPS58501485 A JP S58501485A
Authority
JP
Japan
Prior art keywords
layer
region
substrate
dielectric layer
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57502848A
Other languages
English (en)
Japanese (ja)
Other versions
JPH058572B2 (enExample
Inventor
オニグフオード，エドワードハーバート
ダーム，ヴイノドクマー
Original Assignee
エヌ・シー・アール・インターナショナル・インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エヌ・シー・アール・インターナショナル・インコーポレイテッド filed Critical エヌ・シー・アール・インターナショナル・インコーポレイテッド
Publication of JPS58501485A publication Critical patent/JPS58501485A/ja
Publication of JPH058572B2 publication Critical patent/JPH058572B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10D64/0113—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP57502848A 1981-09-14 1982-09-09 半導体基板の領域間に電気接触部を形成する方法 Granted JPS58501485A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/301,557 US4397076A (en) 1981-09-14 1981-09-14 Method for making low leakage polycrystalline silicon-to-substrate contacts
US301557 1981-09-14

Publications (2)

Publication Number Publication Date
JPS58501485A true JPS58501485A (ja) 1983-09-01
JPH058572B2 JPH058572B2 (enExample) 1993-02-02

Family

ID=23163903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57502848A Granted JPS58501485A (ja) 1981-09-14 1982-09-09 半導体基板の領域間に電気接触部を形成する方法

Country Status (5)

Country Link
US (1) US4397076A (enExample)
EP (1) EP0087472B1 (enExample)
JP (1) JPS58501485A (enExample)
DE (1) DE3277152D1 (enExample)
WO (1) WO1983001152A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698900A (en) * 1986-03-27 1987-10-13 Texas Instruments Incorporated Method of making a non-volatile memory having dielectric filled trenches
US5126285A (en) * 1990-07-02 1992-06-30 Motorola, Inc. Method for forming a buried contact
US5236852A (en) * 1992-09-24 1993-08-17 Motorola, Inc. Method for contacting a semiconductor device
TW250580B (en) * 1994-08-16 1995-07-01 Holtek Microelectronics Inc Layout method
US5629235A (en) * 1995-07-05 1997-05-13 Winbond Electronics Corporation Method for forming damage-free buried contact
US5773346A (en) * 1995-12-06 1998-06-30 Micron Technology, Inc. Semiconductor processing method of forming a buried contact
JP3539887B2 (ja) * 1999-04-09 2004-07-07 沖電気工業株式会社 半導体装置及びその製造方法
KR100348317B1 (ko) * 2000-11-14 2002-08-10 주식회사 하이닉스반도체 반도체 소자 및 그 제조방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052229A (en) * 1976-06-25 1977-10-04 Intel Corporation Process for preparing a substrate for mos devices of different thresholds
JPS54128689A (en) * 1978-03-27 1979-10-05 Intel Corp Method of forming contact area between polycrystal sllicon layers
US4246044A (en) * 1978-07-05 1981-01-20 Tokyo Shibaura Denki Kabushiki Kaisha Method for fabricating semi-conductor devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127931A (en) * 1974-10-04 1978-12-05 Nippon Electric Co., Ltd. Semiconductor device
JPS5284981A (en) * 1976-01-06 1977-07-14 Mitsubishi Electric Corp Production of insulated gate type semiconductor device
US4138782A (en) * 1976-09-16 1979-02-13 International Business Machines Corporation Inverter with improved load line characteristic
US4192059A (en) * 1978-06-06 1980-03-11 Rockwell International Corporation Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process
US4341009A (en) * 1980-12-05 1982-07-27 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052229A (en) * 1976-06-25 1977-10-04 Intel Corporation Process for preparing a substrate for mos devices of different thresholds
US4052229B1 (enExample) * 1976-06-25 1985-01-15
JPS54128689A (en) * 1978-03-27 1979-10-05 Intel Corp Method of forming contact area between polycrystal sllicon layers
US4246044A (en) * 1978-07-05 1981-01-20 Tokyo Shibaura Denki Kabushiki Kaisha Method for fabricating semi-conductor devices

Also Published As

Publication number Publication date
US4397076A (en) 1983-08-09
WO1983001152A1 (en) 1983-03-31
EP0087472A1 (en) 1983-09-07
EP0087472A4 (en) 1985-04-25
EP0087472B1 (en) 1987-09-02
JPH058572B2 (enExample) 1993-02-02
DE3277152D1 (en) 1987-10-08

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