JPS5845850B2 - Kukeihanohakouchigen Cairo - Google Patents
Kukeihanohakouchigen CairoInfo
- Publication number
- JPS5845850B2 JPS5845850B2 JP50147624A JP14762475A JPS5845850B2 JP S5845850 B2 JPS5845850 B2 JP S5845850B2 JP 50147624 A JP50147624 A JP 50147624A JP 14762475 A JP14762475 A JP 14762475A JP S5845850 B2 JPS5845850 B2 JP S5845850B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- rectangular wave
- level
- peak value
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
本発明は一定レベルをもった矩形波を、任意の電圧レベ
ルをもった制御入力信号に応じた波高値をもった矩形波
に制限する、矩形波の波高値制限回路に関するものであ
る。Detailed Description of the Invention The present invention provides a rectangular wave peak value limiting circuit that limits a rectangular wave having a constant level to a rectangular wave having a peak value corresponding to a control input signal having an arbitrary voltage level. It is related to.
インピーダンス変換(バッファ)には、例えば特公昭4
6−15190号公報に示すようなトランジスタを使用
したエミッタフォロアが使われる。For impedance conversion (buffer), for example,
An emitter follower using a transistor as shown in Japanese Patent No. 6-15190 is used.
エミッタフォロアは温度変化に対応する入力電圧■IN
がOであっても、エミッタの電圧vBEは一2mV/℃
程度の温度特性があるので、エミッタの出力電圧Von
tも一2mV/℃程度の温度特性をもつ。The emitter follower has an input voltage ■IN that responds to temperature changes.
Even if is O, the emitter voltage vBE is -2mV/℃
Since the emitter output voltage Von
t also has a temperature characteristic of about -2 mV/°C.
したがって、温度特性を向上させるためには、他の部分
でこれを補償する以外になく、回路が複雑となる。Therefore, the only way to improve the temperature characteristics is to compensate for this in other parts, which makes the circuit complicated.
本発明の目的は任意の電圧レベルをもった制御入力信号
に応じた波高値を有する矩形波を得るために、構成が簡
単でより温度特性の少ない矩形波の波高値制限回路を得
ることにある。An object of the present invention is to obtain a rectangular wave peak value limiting circuit with a simple configuration and less temperature characteristics in order to obtain a rectangular wave having a peak value corresponding to a control input signal having an arbitrary voltage level. .
このため、本発明の構成は演算増幅器からなるボルテー
ジフォロア回路と、該ボルテージフォロア回路の出力側
に抵抗を介してコレクタを接続されたトランジスタから
なるスイッチング回路とを備え、前記ボルテージフォロ
ア回路の入力側に矩形波の波高値を制御する電圧を印加
し、前記スイッチング回路のトランジスタのベース側に
基準の矩形波を印加し、コレクタ側から前記制御電圧に
対応した波高値をもつ矩形波を得るようにしたものであ
る。For this reason, the configuration of the present invention includes a voltage follower circuit made of an operational amplifier, and a switching circuit made of a transistor whose collector is connected to the output side of the voltage follower circuit via a resistor, and the input side of the voltage follower circuit is A voltage for controlling the peak value of a rectangular wave is applied to the transistor, a reference rectangular wave is applied to the base side of the transistor of the switching circuit, and a rectangular wave having a peak value corresponding to the control voltage is obtained from the collector side. This is what I did.
本発明の構成を実施例に基づいて説明すると、第1図に
おいて、1は演算増幅器8と抵抗9からなるボルテージ
フォロア回路、3は矩形波の波高値を制限する任意の電
圧レベルをもった制御電圧の入力端子、6はボルテージ
フォロア回路1の出力端子である。To explain the configuration of the present invention based on an embodiment, in FIG. 1, 1 is a voltage follower circuit consisting of an operational amplifier 8 and a resistor 9, and 3 is a control with an arbitrary voltage level that limits the peak value of a rectangular wave. A voltage input terminal 6 is an output terminal of the voltage follower circuit 1.
2はトランジスタ13と抵抗10゜11.12からなる
スイッチング回路、4は一定電圧レベルの矩形波の入力
端子、5は任意の電圧レベルに制限された波高値をもっ
た矩形波の出力端子である。2 is a switching circuit consisting of a transistor 13 and a resistor 10°11.12; 4 is an input terminal for a rectangular wave with a constant voltage level; and 5 is an output terminal for a rectangular wave with a peak value limited to an arbitrary voltage level. .
第2図において、■はOレベルとEレベルをもった矩形
波で、端子4に印加される。In FIG. 2, ■ is a rectangular wave having an O level and an E level, and is applied to the terminal 4.
■はVcのレベルをもった制御電圧で、端子3に印加さ
れる。2 is a control voltage having the level of Vc, which is applied to the terminal 3.
■はOのレベルとVcのレベルをもった矩形波で、波高
値Vcに制限されて端子5から出力される。3 is a rectangular wave having the O level and the Vc level, and is output from the terminal 5 with the wave height limited to the peak value Vc.
上述の回路構成において、端子3に■に示すようなVo
のレベルをもった電圧を印加すると、端子6には演算増
幅器8がボルテージフォロアを形成しているので、同一
電圧レベルのVcが得られる。In the above circuit configuration, the terminal 3 is connected to Vo as shown in ■.
When a voltage having a level of is applied to the terminal 6, since the operational amplifier 8 forms a voltage follower at the terminal 6, the same voltage level Vc is obtained.
そして、端子4に■に示すようなOレベルとEレベルを
もった矩形波を印加すると、端子5にはIに示す矩形波
のレベルがOの間は、スイッチング回路2のトランジス
タ13は不導通であるので、Vcのレベルの電圧が得ら
れる。Then, when a rectangular wave having an O level and an E level as shown in ■ is applied to the terminal 4, the transistor 13 of the switching circuit 2 is non-conductive while the level of the rectangular wave shown in I is O. Therefore, a voltage at the level of Vc can be obtained.
矩形波のレベルがEの間はトランジスタ13は導通であ
るので、レベルはOとなる。Since the transistor 13 is conductive while the level of the rectangular wave is E, the level becomes O.
結局■に示すようにOレベルとVcレベルをもった矩形
波が得られる。Eventually, a rectangular wave having an O level and a Vc level is obtained as shown in (3).
本発明では、トランジスタ13を飽和増幅させて使用し
ているので、トランジスタ13が導通状態にあるときの
コレクタ電圧VOEは20〜30mV程度に抑えるえる
ことができ、この電圧VORに温度特性があったとして
も問題にならない。In the present invention, since the transistor 13 is used with saturation amplification, the collector voltage VOE when the transistor 13 is in a conductive state can be suppressed to about 20 to 30 mV, and this voltage VOR has a temperature characteristic. Even so, it's not a problem.
なぜなら、飽和増幅の場合、エミッタ電圧VOEの温度
特性は、一般に電圧VOEの+0.5%/℃程度であり
、したがって、電圧VOEを20〜30mVとすると、
温度特性は100〜150μV/’C(0,1〜0.1
5 TrLVloC)となり、エミツクフオロアの場合
のベース電圧VBEの温度特性よりも1桁以上小さくな
る。This is because, in the case of saturated amplification, the temperature characteristic of the emitter voltage VOE is generally about +0.5%/°C of the voltage VOE, so if the voltage VOE is 20 to 30 mV,
Temperature characteristics are 100~150μV/'C (0.1~0.1
5TrLVloC), which is more than one order of magnitude smaller than the temperature characteristic of the base voltage VBE in the case of an emitter follower.
上述のように、本発明によれば電源の利用率および温度
特性などが良好な桁形波の波高値制限回路を安価に提供
できるという効果が得られる。As described above, according to the present invention, it is possible to provide, at a low cost, a peak value limiting circuit for an digit wave with good power supply utilization rate, temperature characteristics, and the like.
第1図は本発明に係る波高値制限回路の電気結線図、第
2図は同回路の入出力波形である。
1・・・・・・ボルテージフォロア回路、2・・・・・
・スイッチング回路、8・・・・・・演算増幅器、13
・・・・・・トランジスタ。FIG. 1 is an electrical wiring diagram of a peak value limiting circuit according to the present invention, and FIG. 2 is an input/output waveform of the circuit. 1... Voltage follower circuit, 2...
・Switching circuit, 8... Operational amplifier, 13
...Transistor.
Claims (1)
ボルテージフォロア回路の出力側に抵抗を介してコレク
タを接続されたトランジスタからなるスイッチング回路
とを備え、前記ボルテージフォロア回路の入力側に矩形
波の波高値を制御する電圧を印加し、前記スイッチング
回路のトランジスタのベース側に基準の矩形波を印加し
、コレクタ側から前記制御電圧に対応した波高値をもつ
矩形波を得るようにしたことを特徴とする矩形波の波高
値制限回路。1 A voltage follower circuit consisting of an operational amplifier, and a switching circuit consisting of a transistor whose collector is connected to the output side of the voltage follower circuit via a resistor, and the peak value of a rectangular wave is input to the input side of the voltage follower circuit. A rectangular waveform is characterized in that a voltage to be controlled is applied, a reference rectangular wave is applied to the base side of the transistor of the switching circuit, and a rectangular wave having a peak value corresponding to the control voltage is obtained from the collector side. Wave peak value limiting circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50147624A JPS5845850B2 (en) | 1975-12-11 | 1975-12-11 | Kukeihanohakouchigen Cairo |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50147624A JPS5845850B2 (en) | 1975-12-11 | 1975-12-11 | Kukeihanohakouchigen Cairo |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5286756A JPS5286756A (en) | 1977-07-19 |
JPS5845850B2 true JPS5845850B2 (en) | 1983-10-13 |
Family
ID=15434524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50147624A Expired JPS5845850B2 (en) | 1975-12-11 | 1975-12-11 | Kukeihanohakouchigen Cairo |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5845850B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5656036A (en) * | 1979-10-12 | 1981-05-16 | Hitachi Ltd | Pulse driving circuit |
JPS58144925U (en) * | 1982-03-26 | 1983-09-29 | 株式会社日立製作所 | D/A conversion circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49116943A (en) * | 1973-03-09 | 1974-11-08 | ||
JPS5042687U (en) * | 1973-08-16 | 1975-04-30 |
-
1975
- 1975-12-11 JP JP50147624A patent/JPS5845850B2/en not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49116943A (en) * | 1973-03-09 | 1974-11-08 | ||
JPS5042687U (en) * | 1973-08-16 | 1975-04-30 |
Also Published As
Publication number | Publication date |
---|---|
JPS5286756A (en) | 1977-07-19 |
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