JPS60148207A - Differential amplifier circuit with clamp circuit - Google Patents

Abstract

PURPOSE:To prevent generation of delay to an output by clamping the output with an integral number of multiple of a base-emitter voltage of a transistor (TR) so as to eliminate the saturation of the TR. CONSTITUTION:Diodes 9-11 are inserted in series between an output terminal Vout and a common emitter of TRs 5, 6, and diodes 13, 14 and a resistor 12 are connected in series between a power terminal VCC and a reference voltage 2. When the amplitude of a signal source 1 is large, the higher voltage of the output is clamped to a voltage from the voltage of the common emitter of the TRs 5, 6 increased by 3 times the base-emitter voltage VBE of the TRs 5, 6 and the lower voltage is clamped to a voltage from the voltage 2 decreased by 2 times the VBE respectively so as not to saturate the TRs 4, 6.

Description

[Detailed Description of the Invention] [Background and Objectives of the Invention] The present invention relates to a differential amplifier circuit with a clamp circuit, and is particularly suitable for eliminating output delay and eliminating power supply voltage dependence of the output. It is connected to a differential amplifier circuit with a lamp circuit.

FIG. 1 is a circuit diagram showing an example of a differential amplifier circuit known from the prior art. In Figure 1, l is a signal source, 2 is a reference voltage, 3.4 is a PNP) transistor, and 5.6 is an N
PN) Transistor 9.7 is a constant current source, and transistor 5
and 6 with transistors 3 and 4 as loads,
It is a differential amplifier circuit driven by a constant current source 7, and is configured to compare the signal source 1 and the reference voltage 2 and amplify the difference. The circuit shown in Fig. 1 consists of PNP) transistor 3
Since it uses a dynamic load of 4°, the gain of the circuit is large, and it is widely used for amplifying small signals.

However, if a signal with a large amplitude that switches the currents of transistors 5 and 6 is applied to this circuit, the output Vout% increases, and the amplitude changes between the common base voltage v1 of transistor 3.4 and the reference voltage. If the potential difference exceeds v2, transistors 4 and 6 will be saturated, causing a problem that the rise of the output waveform will be delayed.

The present invention has been made in view of the above, and an object thereof is to provide a differential circuit with a clamp circuit that can prevent transistors from becoming saturated and output delays from occurring. be.

[Summary of the invention]

The feature of the present invention is that when a large-amplitude signal that switches the current flowing through a pair of transistors with a common emitter is input, the higher output voltage is
The circuit configuration is such that the lower voltage is clamped to a voltage that is an integer multiple of the base-emitter voltage of each transistor relative to the reference voltage that serves as the reference for the signal source.

〔Example〕

The present invention will be explained in detail below using the embodiment shown in FIG.

FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit with a clamp circuit according to the present invention. The same parts as those in FIG. In FIG. 2, a diode 9610.11 is inserted in series between the output terminal Vout and the common emitter of NPN transistors 5 and 6, and a resistor 12.11 is inserted between the power supply voltage terminal Vcc and the reference voltage 2. Diodes 13 and 14 are connected in series, and a transistor 80 is connected to the connection point between resistor 12 and diode 13.
The base of this transistor 8 is connected, the emitter of this transistor 8 is connected to the output terminal Vout, and the collector is connected to the power supply voltage terminal Vcc.

In the circuit shown in FIG. 2, when the amplitude of signal source 1 is large, the higher voltage of its output Vout is higher than the voltage at the common emitter of transistors 5 and 6.
．． The lower voltage is 2 VBE higher than the reference voltage 2, that is, the voltage is 1 VBE lower than the above voltage. clamped, i.e. the output Vou
t is clamped to a voltage one VBE higher than the reference voltage to prevent transistors 4 or 6 from becoming saturated.

As described above, according to the embodiment of the present invention, the output can be clamped at an integral multiple of the base-emitter voltage VBE of the transistor, and the transistor 3.4 can be prevented from operating in saturation. It is possible to avoid this delay. Also, its output no longer depends on the power supply voltage.

〔Effect of the invention〕

As described above, according to the present invention, there is an effect that the transistor does not become saturated and the output delay does not occur.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional differential amplifier circuit, and FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit with a clamp circuit according to the present invention. l: signal source, 2: reference voltage. 3 to 6.8:) transistor, 7: constant current source. 9-11.13.14: Diode, 12: Resistor. Figure 1 No. 21￥l

Claims (1)

[Claims] 0) In a differential amplifier circuit consisting of another pair of transistors with common emitters and having a dynamic load consisting of two pairs of transistors that compare a signal source and a reference voltage and amplify the difference, the pair of transistors with common emitters When a large amplitude signal that switches the current flowing in the output is input, the higher voltage of the output is higher than the common emitter, and the lower voltage is lower than the reference voltage by an integer multiple of the base-emitter voltage of the transistor. 1. A differential amplifier circuit with a clamp circuit, characterized by comprising means for clamping to an increased voltage.