JPS6231523B2 - - Google Patents

Info

Publication number
JPS6231523B2
JPS6231523B2 JP53084173A JP8417378A JPS6231523B2 JP S6231523 B2 JPS6231523 B2 JP S6231523B2 JP 53084173 A JP53084173 A JP 53084173A JP 8417378 A JP8417378 A JP 8417378A JP S6231523 B2 JPS6231523 B2 JP S6231523B2
Authority
JP
Japan
Prior art keywords
transistor
terminal
amplifier
base
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53084173A
Other languages
Japanese (ja)
Other versions
JPS5511640A (en
Inventor
Masashi Shoji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8417378A priority Critical patent/JPS5511640A/en
Publication of JPS5511640A publication Critical patent/JPS5511640A/en
Publication of JPS6231523B2 publication Critical patent/JPS6231523B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明は電力増幅器に関し、特にその入力回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to power amplifiers, and more particularly to input circuits thereof.

従来、単一電源より電圧供給される電力増幅器
において、入力信号印加端子にエミツタホロアト
ランジスタのベースを接続し、そのエミツタから
信号を出力しこの出力信号を後段増幅器に印加す
るようにし、入力信号印加端子の直流電圧をほぼ
接地電圧付近に設定して信号源と入力信号印加端
子間の直流差電圧をほぼ零とし、それらの間に直
流阻止用コンデンサを介さず直接接続とする入力
回路を備えることが行われているが、これは部品
数の減少をもたらしコスト及び高密度実装の面で
有利な技術である。
Conventionally, in a power amplifier that is supplied with voltage from a single power supply, the base of an emitter-follower transistor is connected to the input signal application terminal, a signal is output from the emitter, and this output signal is applied to the subsequent amplifier. An input circuit is constructed in which the DC voltage of the signal application terminal is set to approximately the ground voltage, the DC voltage difference between the signal source and the input signal application terminal is almost zero, and there is a direct connection between them without a DC blocking capacitor. This technique reduces the number of components and is advantageous in terms of cost and high-density packaging.

従来、このような電力増幅器は第1図に示す如
く、入力端子2に加えられた入力信号は、エミツ
タホロアトランジスタ12を通して差動増幅器を
構成するトランジスタ14で増幅された後、入力
段の出力端子3を通して前置駆動トランジスタ2
2に加えられ、トランジスタ22で増幅された
後、相補トランジスタ構成25および26からな
るシングルエンデツドプツシユプル回路から出力
されて、出力端子5に現われる。トランジスタ1
2のベースは入力端子2に接続されると共に抵抗
8を介してそのコレクタと共通に接地端子6に接
続されており、そのエミツタはトランジスタ14
のベースに接続されると共に抵抗9を介して電源
端子4及び接地端子6間の定電圧回路を構成する
抵抗18、ツエナーダイオード19の接続点に接
続されており、トランジスタ14と15と抵抗1
3とで差動増幅器を構成し、トランジスタ14の
コレクタは負荷抵抗16を介して接地端子6に接
続されると共に出力端子3に接続されている。前
置駆動トランジスタ22のコレクタは、ダイオー
ドを複数個(この場合は3個)逆方向に直列に接
続したレベルシフト回路24と抵抗23を通して
電源端子4に接続されており、レベルシフト回路
の両端にはダーリントン接続した相補トランジス
タ構成25,26のベース相当の端子が接続され
ており、そのエミツタ相当の端子は出力端子5に
共通接続されている。抵抗20に定電流源17よ
り一定電流が流れ、出力端子5の直流電圧がレベ
ルシフトされてトランジスタ15のベースに加え
られると共にNF端子1と接地間に抵抗、コンデ
ンサを直列接続して(図示せず)抵抗20とで負
帰還回路が形成されている。入力端子2の直流電
圧はトランジスタ12のベース電流と抵抗8によ
り定まり、その値は容易に接地電圧付近となり信
号源eiと入力端子2は直接接続されている。
Conventionally, in such a power amplifier, as shown in FIG. 1, an input signal applied to an input terminal 2 is amplified by a transistor 14 constituting a differential amplifier through an emitter follower transistor 12, and then amplified by a transistor 14 constituting a differential amplifier. Predrive transistor 2 through output terminal 3
After being amplified by transistor 22, it is output from a single-ended push-pull circuit consisting of complementary transistor arrangements 25 and 26 and appears at output terminal 5. transistor 1
The base of 2 is connected to the input terminal 2, and its collector and common ground terminal 6 are connected via a resistor 8, and the emitter of the transistor 14 is connected to the ground terminal 6.
It is connected via a resistor 9 to the connection point of a resistor 18 and a Zener diode 19, which constitute a constant voltage circuit between the power supply terminal 4 and the ground terminal 6.
3 constitute a differential amplifier, and the collector of the transistor 14 is connected to the ground terminal 6 via a load resistor 16 and also to the output terminal 3. The collector of the front drive transistor 22 is connected to the power supply terminal 4 through a level shift circuit 24 having a plurality of diodes (three in this case) connected in series in opposite directions and a resistor 23. are connected to terminals corresponding to the bases of complementary transistor structures 25 and 26 connected in a Darlington manner, and terminals corresponding to the emitters thereof are commonly connected to the output terminal 5. A constant current flows through the resistor 20 from the constant current source 17, and the DC voltage at the output terminal 5 is level-shifted and applied to the base of the transistor 15. A resistor and a capacitor are connected in series between the NF terminal 1 and the ground (not shown). (1) A negative feedback circuit is formed with the resistor 20. The DC voltage at the input terminal 2 is determined by the base current of the transistor 12 and the resistor 8, and its value is easily close to the ground voltage, so that the signal source ei and the input terminal 2 are directly connected.

かかる電力増幅器に於いて、信号源eiより入力
端子2に印加された入力信号は、トランジスタ1
4,15で構成された差動増幅器で増幅された
後、出力端子3に出力される出力信号とは通常オ
ーデイオ周波数の範囲で逆相となり、正の半サイ
クルの入力信号時は出力端子3の出力信号は負の
半サイクルとなり、負の半サイクルの入力信号時
は正の半サイクルの出力信号となる。このことは
負の半サイクルの入力信号印加時はトランジスタ
12のベースおよびエミツタ、トランジスタ14
のベースおよびエミツタが負側に振られ出力端子
3すなわちトランジスタ14のコレクタは正側に
振られることとなり、入力信号が大きくなればそ
れらの振幅も大きくなり、トランジスタ14のエ
ミツタ・コレクタ間の電圧差が小さくなる。更に
負の半サイクルの入力信号が増大するとトランジ
スタ14は飽和してしまい、そのコレクタ電圧は
そのエミツタ電圧より高く振れることはなく、エ
ミツタ電圧により規制されることとなり、そのエ
ミツタ電圧は入力信号に応答して振られるため入
力信号が過大となると、その負の半サイクル時の
出力端子3の出力信号は、正の半サイクル時に負
側に振られることとなり、入力信号の負の半サイ
クル時に導通状態であるべき前置駆動トランジス
タ22が非導通あるいはドライブ不足となつてし
まり、相補トランジスタ構成26が非導通又は、
ドライブ不足となつてしまう。以上の様に小入力
信号時は正負半サイクルごとにそれぞれ相補トラ
ンジスタ構成25又は26が応答して導通、非導
通を繰り返しているが、過大入力信号の負の半サ
イクル時に相補トランジスタ構成26が非導通と
なり、出力端子5より出力される出力波形は第4
図aの正常波形に対し、第4図bの如き異常波形
となる。
In such a power amplifier, an input signal applied to the input terminal 2 from the signal source ei is transmitted to the transistor 1.
After being amplified by the differential amplifier composed of 4 and 15, the output signal output to output terminal 3 is normally in the opposite phase within the audio frequency range, and when the input signal is in a positive half cycle, the output signal of output terminal 3 is The output signal is a negative half cycle, and when the input signal is a negative half cycle, the output signal is a positive half cycle. This means that when a negative half-cycle input signal is applied, the base and emitter of transistor 12,
The base and emitter of the transistor 14 are swung to the negative side, and the output terminal 3, that is, the collector of the transistor 14, is swung to the positive side.As the input signal becomes larger, their amplitude also increases, and the voltage difference between the emitter and collector of the transistor 14 increases. becomes smaller. If the negative half-cycle input signal increases further, the transistor 14 will become saturated, and its collector voltage will not swing higher than its emitter voltage, but will be regulated by the emitter voltage, which will respond to the input signal. Therefore, if the input signal becomes excessive, the output signal of output terminal 3 during the negative half cycle will swing to the negative side during the positive half cycle, and the input signal will be in a conductive state during the negative half cycle. Predrive transistor 22 becomes non-conducting or underdriven, and complementary transistor arrangement 26 becomes non-conducting or
This results in a lack of drive. As described above, when the input signal is small, the complementary transistor configuration 25 or 26 responds to each positive and negative half cycle and repeats conduction and non-conduction, but when the input signal is large, the complementary transistor configuration 26 becomes non-conductive during the negative half cycle. It becomes conductive, and the output waveform output from the output terminal 5 is the fourth one.
In contrast to the normal waveform shown in Fig. 4(a), an abnormal waveform as shown in Fig. 4(b) appears.

本発明は上述の如き従来の欠点に鑑み、簡単な
回路構成で負の過大入力信号時の下側相補トラン
ジスタ構成26の非導通となることを防止した良
好な電力増幅器を得ることを目的とする。
In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a good power amplifier with a simple circuit configuration that prevents the lower complementary transistor structure 26 from becoming non-conductive when an excessively negative input signal is applied. .

本発明によれば、ベースに入力される入力信号
で駆動されるエミツタホロアトランジスタと該ト
ランジスタの出力を増幅する増幅器と、該増幅器
の出力信号を増幅する前置駆動増幅器と前置駆動
増幅器の出力を電流増幅するプツシユプル回路と
を備えた電力増幅器に於て、前記エミツタホロア
トランジスタのベースを第1の抵抗でベースバイ
アスを供給すると共に第2の抵抗を通して入力印
加端子に接続し、該入力端子に加える負の過大入
力信号電流の一部を前記エミツタホロアトランジ
スタのコレクタ・ベース間順方向電流で前記第2
の抵抗を通して供給し、前記エミツタホロアトラ
ンジスタのベース電位を接地電位よりコレクタ・
ベース間順方向電圧だけ低い電位に規制し、該ベ
ース電位で前記前置駆動増幅器が導通させるよう
に、前記エミツタホロアトランジスタと前記増幅
器の入力端子間に直流電圧をレベルシフトする手
段を設けたことを特徴とする電力増幅器を得る。
According to the present invention, an emitter follower transistor driven by an input signal input to a base, an amplifier that amplifies the output of the transistor, a predrive amplifier and a predrive amplifier that amplify the output signal of the amplifier. In the power amplifier equipped with a push-pull circuit for current amplifying the output of the emitter-follower transistor, the base of the emitter-follower transistor is connected to an input application terminal through a first resistor to supply a base bias, and through a second resistor; A part of the excessive negative input signal current applied to the input terminal is converted into the collector-base forward current of the emitter follower transistor by the second transistor.
is supplied through the resistor, and the base potential of the emitter follower transistor is lowered from the collector potential to the ground potential.
Means is provided for level shifting the DC voltage between the emitter follower transistor and the input terminal of the amplifier so that the forward voltage between the bases is regulated to a lower potential and the predrive amplifier is made conductive at the base potential. The present invention provides a power amplifier characterized in that:

以下本発明を図面を参照して詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.

第2図は本発明の一実施例を示し、第1図と同
じものは同符号を用いており、異なるところはエ
ミツタホロアトランジスタ12のベースを抵抗7
を通して入力端子2に接続し、そのエミツタは逆
方向のダイオード10を通してトランジスタ14
のベース及び抵抗9に接続していることである。
入力端子2に小信号が加えられると抵抗7を通し
てトランジスタ12のベースに加えられ、抵抗7
に対して抵抗8及びトランジスタ12のベース側
からエミツタ側をみたインピーダンスは充分に大
きいため信号の損失は無視でき、トランジスタ1
2のエミツタを通した信号はダイオード10を通
してトランジスタ14のベースに加えられ、ダイ
オード10の動抵抗に対し抵抗9及びトランジス
タ14のベース側からエミツタ側をみたインピー
ダンスは充分大きく、信号損失はなく第1図の従
来の電力増幅器と同様に動作する。入力端子2に
負の過大信号が加えられ、これがトランジスタ1
2のコレクタ・ベース順方向電圧より大きくなる
と信号電流の一部としてトランジスタ12のコレ
クタ・ベース順方向電流が抵抗7を通して供給さ
れる結果、トランジスタ12のベース電位は接地
電位(トランジスタ12のコレクタ電位)よりコ
レクタ・ベース順方向電圧だけ低い電位に規制さ
れ、それ以上の低い電位となることを抑制され
る。このベース電位においてトランジスタ14の
ベース電位は、トランジスタ12のコレクタ・ベ
ース順方向電圧とエミツタ・ベース順方向電圧と
ダイオード10の順方向電圧はほぼ等しいため、
順方向の接合電圧だけ接地電位より高く、通常ト
ランジスタのエミツタ・コレクタ間飽和電圧は小
電流において順方向接合電圧よりも小さいため、
トランジスタ14は飽和することなく前置駆動ト
ランジスタ22が非導通あるいはドライブ不足と
ならず、相補トランジスタ構成26も非導通ある
いはドライブ不足とはならず、入力信号の大きさ
にかかわらず負の入力信号印加時は相補トランジ
スタ構成26が無論正の入力信号印加時は相補ト
ランジスタ構成25が導通し、従来のような異常
波形を防止することができる。ここではトランジ
スタ14のエミツタ・コレクタ間飽和電圧が順方
向接合電圧よりも小さいとしたが、仮に順方向接
合電圧よりも大きい場合にはトランジスタ14が
飽和しない様トランジスタ14のベースとトラン
ジスタ12のエミツタ間にダイオード10と直列
接続したダイオードを追加接続すれば良い。
FIG. 2 shows an embodiment of the present invention, in which the same parts as in FIG.
is connected to the input terminal 2 through the transistor 14, and its emitter is connected to the transistor 14 through the reverse diode 10.
is connected to the base of the resistor 9 and the resistor 9.
When a small signal is applied to input terminal 2, it is applied to the base of transistor 12 through resistor 7, and is applied to the base of transistor 12 through resistor 7.
Since the impedance of the resistor 8 and the transistor 12 seen from the base side to the emitter side is sufficiently large, the signal loss can be ignored.
The signal passed through the emitter of No. 2 is applied to the base of the transistor 14 through the diode 10, and the impedance seen from the base side of the resistor 9 and the transistor 14 to the emitter side is sufficiently large compared to the dynamic resistance of the diode 10, and there is no signal loss. It operates similarly to the conventional power amplifier shown in the figure. A negative excessive signal is applied to input terminal 2, which causes transistor 1 to
2, the collector-base forward current of transistor 12 is supplied through resistor 7 as part of the signal current, and as a result, the base potential of transistor 12 becomes ground potential (collector potential of transistor 12). The potential is regulated to be lower by the collector-base forward voltage, and the potential is prevented from becoming lower than that. At this base potential, the base potential of the transistor 14 is approximately equal to the collector-base forward voltage, the emitter-base forward voltage of the transistor 12, and the forward voltage of the diode 10.
Only the forward junction voltage is higher than the ground potential, and normally the emitter-collector saturation voltage of a transistor is smaller than the forward junction voltage at a small current.
Transistor 14 does not saturate, predrive transistor 22 does not become non-conducting or under-driven, and complementary transistor configuration 26 does not become non-conducting or under-driven, so that a negative input signal is applied regardless of the magnitude of the input signal. Of course, when a positive input signal is applied to the complementary transistor structure 26, the complementary transistor structure 25 becomes conductive, and an abnormal waveform as in the conventional case can be prevented. Here, it is assumed that the emitter-collector saturation voltage of the transistor 14 is smaller than the forward junction voltage, but if it is larger than the forward junction voltage, the voltage between the base of the transistor 14 and the emitter of the transistor 12 is A diode connected in series with the diode 10 may be additionally connected to the diode 10.

第3図は本発明の他の実施例であつて、第2図
の実施例と同一のものは同一符号を用いており、
異なる点はダイオード10とトランジスタ12の
エミツタ間に順方向のダイオード11を接続して
おり、前置駆動増幅器をトランジスタ21,22
をダーリントン接続して構成しており、入力段の
出力端子3から前置駆動増幅器側をみたインピー
ダンスを高くした電力増幅器に本発明を実施した
ことである。前置駆動増幅器をダーリントン接続
のトランジスタ21,22で構成することにより
出力端子3の出力信号振幅を大きくとる必要があ
り、第2図の実施例に較べトランジスタ21のベ
ース・エミツタ間順方向電圧分をダイオード11
の順方向電圧だけトランジスタ14のベース電位
をレベルシフトして得ている。この実施例におい
ても第2図の実施例と同様の本発明の効果を得る
ことができる。又、第2図、第3図の実施例に於
て、入力端子2とトランジスタ12のベース間に
抵抗7を接続しているが、入力信号電流が小さく
その信号電流の範囲でトランジスタ12のコレク
タ・ベース間順方向電圧が著しく変化しない場合
には抵抗7を削除してもトランジスタ12のベー
ス電位は、接地電位よりそのコレクタ・ベース間
順方向電圧だけ低い電位に規制され、上述の効果
が得られる。
FIG. 3 shows another embodiment of the present invention, in which the same parts as in the embodiment of FIG. 2 are given the same reference numerals.
The difference is that a forward diode 11 is connected between the diode 10 and the emitter of the transistor 12, and the pre-drive amplifier is connected to the transistors 21 and 22.
The present invention is implemented in a power amplifier which has a Darlington connection, and has a high impedance when viewed from the output terminal 3 of the input stage to the predrive amplifier side. By configuring the pre-drive amplifier with Darlington-connected transistors 21 and 22, it is necessary to increase the amplitude of the output signal at the output terminal 3, and compared to the embodiment shown in FIG. 2, the forward voltage between the base and emitter of the transistor 21 is the diode 11
It is obtained by level-shifting the base potential of the transistor 14 by a forward voltage of . In this embodiment as well, the same effects of the present invention as in the embodiment shown in FIG. 2 can be obtained. In the embodiments shown in FIGS. 2 and 3, a resistor 7 is connected between the input terminal 2 and the base of the transistor 12, but the input signal current is small and the collector of the transistor 12 is connected within the range of the signal current. - If the base-to-base forward voltage does not change significantly, even if the resistor 7 is removed, the base potential of the transistor 12 will be regulated to a potential lower than the ground potential by the collector-base forward voltage, and the above effect will not be obtained. It will be done.

以上の如く、本発明によれば非常に簡単な構成
で過大な入力信号印加に対しても正負の半サイク
ルごとに入力信号に応じて、出力段のプツシユプ
ル回路が正常に動作する電力増幅器を実現するこ
とができる。
As described above, according to the present invention, it is possible to realize a power amplifier with a very simple configuration in which the push-pull circuit in the output stage operates normally according to the input signal every positive and negative half cycle even when an excessive input signal is applied. can do.

更に本発明は半導体集積回路に応用することも
容易であることは言うまでもない。
Furthermore, it goes without saying that the present invention can be easily applied to semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電力増幅器の回路接続図、第2
図は本発明の一実施例を示す回路接続図、第3図
は本発明の他の実施例を示す回路接続図であり、
第4図aは本発明の実施例の出力端子5の出力波
形、bは従来例の出力端子5の出力波形である。 1……NF端子、2……入力端子、4……電源
端子、5……出力端子、6……接地端子、8,
9,13,16,18,20,23……抵抗、1
2……エミツタホロアトランジスタ、14,15
……差動増幅器を構するトランジスタ、21,2
2……前置駆動トランジスタ、24……レベルシ
フト回路、25,26……相補トランジスタ構
成、7……信号電流制限用抵抗、10,11……
直流電圧レベルシフト用ダイオード、19……ツ
エナーダイオード。
Figure 1 is a circuit connection diagram of a conventional power amplifier, Figure 2 is a circuit diagram of a conventional power amplifier.
The figure is a circuit connection diagram showing one embodiment of the present invention, and FIG. 3 is a circuit connection diagram showing another embodiment of the present invention.
FIG. 4a shows the output waveform of the output terminal 5 of the embodiment of the present invention, and FIG. 4b shows the output waveform of the output terminal 5 of the conventional example. 1...NF terminal, 2...Input terminal, 4...Power terminal, 5...Output terminal, 6...Ground terminal, 8,
9, 13, 16, 18, 20, 23...Resistance, 1
2... Emitsuta follower transistor, 14, 15
...Transistors forming a differential amplifier, 21, 2
2... Front drive transistor, 24... Level shift circuit, 25, 26... Complementary transistor configuration, 7... Signal current limiting resistor, 10, 11...
Diode for DC voltage level shift, 19... Zener diode.

Claims (1)

【特許請求の範囲】[Claims] 1 入力端子と、出力端子と、帰還端子と、電源
端子と、接地端子と、前記入力端子に接続された
入力回路と、前記入力回路の出力信号を増幅する
差動増幅器と、前記差動増幅器の出力信号を増幅
する前置駆動増幅器と、前記前置駆動増幅器の出
力信号を増幅し前記出力端子に出力する相補トラ
ンジスタ構成からなるシングルエンデツドプツシ
ユプル回路を具備し、前記出力端子をバイアス抵
抗を介して前記帰還端子に接続した電力増幅器に
おいて、前記入力回路がエミツタホロワトランジ
スタからなり、前記エミツタホロワトランジスタ
のベースを抵抗を介して入力端子に接続し、エミ
ツタをレベルシフト手段を介して前記差動増幅器
の入力端子に接続したことを特徴とする電力増幅
器。
1: an input terminal, an output terminal, a feedback terminal, a power supply terminal, a ground terminal, an input circuit connected to the input terminal, a differential amplifier that amplifies the output signal of the input circuit, and the differential amplifier a pre-drive amplifier for amplifying an output signal of the pre-drive amplifier; and a single-ended push-pull circuit comprising a complementary transistor configuration for amplifying the output signal of the pre-drive amplifier and outputting the amplified signal to the output terminal, and biasing the output terminal. In the power amplifier connected to the feedback terminal via a resistor, the input circuit includes an emitter follower transistor, the base of the emitter follower transistor is connected to the input terminal via the resistor, and the emitter is connected to level shifting means. A power amplifier, characterized in that the power amplifier is connected to the input terminal of the differential amplifier via the input terminal of the differential amplifier.
JP8417378A 1978-07-10 1978-07-10 Power amplifier Granted JPS5511640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8417378A JPS5511640A (en) 1978-07-10 1978-07-10 Power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8417378A JPS5511640A (en) 1978-07-10 1978-07-10 Power amplifier

Publications (2)

Publication Number Publication Date
JPS5511640A JPS5511640A (en) 1980-01-26
JPS6231523B2 true JPS6231523B2 (en) 1987-07-09

Family

ID=13823092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8417378A Granted JPS5511640A (en) 1978-07-10 1978-07-10 Power amplifier

Country Status (1)

Country Link
JP (1) JPS5511640A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01150154U (en) * 1988-04-04 1989-10-17
JP2018137537A (en) * 2017-02-20 2018-08-30 オンキヨー株式会社 Audio Amplifier and Audio Power Amplifier

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878971A (en) * 1994-06-30 1996-03-22 Fujitsu Ltd Output circuit and arithmetic amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01150154U (en) * 1988-04-04 1989-10-17
JP2018137537A (en) * 2017-02-20 2018-08-30 オンキヨー株式会社 Audio Amplifier and Audio Power Amplifier

Also Published As

Publication number Publication date
JPS5511640A (en) 1980-01-26

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