JPS5844843U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5844843U
JPS5844843U JP1981139983U JP13998381U JPS5844843U JP S5844843 U JPS5844843 U JP S5844843U JP 1981139983 U JP1981139983 U JP 1981139983U JP 13998381 U JP13998381 U JP 13998381U JP S5844843 U JPS5844843 U JP S5844843U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
abstract
semiconductor device
semiconductor element
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981139983U
Other languages
English (en)
Inventor
芳岡　勇行
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1981139983U priority Critical patent/JPS5844843U/ja
Publication of JPS5844843U publication Critical patent/JPS5844843U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図ａ、　　ｂはそれぞれ従来のリードフレームのマ
ウント部の平面図およびＡ−Ａ’断面図、第２図ａ、　
　ｂは夫々穴のあいたリードフレームのマ：　　ラント
部の平面図および断面図であ゛る。 １・・・・・・リードフレームマウント部（アイランド
）、２・・・・・・ＩＣペレット（半導体素子）、３・
・・・・・穴、４・・・・・・マウント材。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子がリードフレームのアイランド部に接着され
    た半導体装置において、上記アイランド部の上記半導体
    素子周辺が位置する部分に少くとも一ケ所以上の穴を有
    することを特徴とする半導体装置。
JP1981139983U 1981-09-21 1981-09-21 半導体装置 Pending JPS5844843U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981139983U JPS5844843U (ja) 1981-09-21 1981-09-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981139983U JPS5844843U (ja) 1981-09-21 1981-09-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS5844843U true JPS5844843U (ja) 1983-03-25

Family

ID=29933158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981139983U Pending JPS5844843U (ja) 1981-09-21 1981-09-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS5844843U (ja)

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