JPS5843020A - 論理装置のリセツト回路 - Google Patents

論理装置のリセツト回路

Info

Publication number
JPS5843020A
JPS5843020A JP56139927A JP13992781A JPS5843020A JP S5843020 A JPS5843020 A JP S5843020A JP 56139927 A JP56139927 A JP 56139927A JP 13992781 A JP13992781 A JP 13992781A JP S5843020 A JPS5843020 A JP S5843020A
Authority
JP
Japan
Prior art keywords
reset
circuit
output
pulse
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56139927A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0157810B2 (enrdf_load_stackoverflow
Inventor
Teruyuki Kubo
久保　輝幸
Kenichi Ishii
賢一 石井
Yuichi Yamazaki
山崎　悠一
Tsuneji Kimeda
木目田　常治
Shinichi Mori
森　真一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56139927A priority Critical patent/JPS5843020A/ja
Publication of JPS5843020A publication Critical patent/JPS5843020A/ja
Publication of JPH0157810B2 publication Critical patent/JPH0157810B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
JP56139927A 1981-09-05 1981-09-05 論理装置のリセツト回路 Granted JPS5843020A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56139927A JPS5843020A (ja) 1981-09-05 1981-09-05 論理装置のリセツト回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56139927A JPS5843020A (ja) 1981-09-05 1981-09-05 論理装置のリセツト回路

Publications (2)

Publication Number Publication Date
JPS5843020A true JPS5843020A (ja) 1983-03-12
JPH0157810B2 JPH0157810B2 (enrdf_load_stackoverflow) 1989-12-07

Family

ID=15256898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56139927A Granted JPS5843020A (ja) 1981-09-05 1981-09-05 論理装置のリセツト回路

Country Status (1)

Country Link
JP (1) JPS5843020A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170622A (ja) * 1984-09-13 1986-04-11 Matsushita Electric Ind Co Ltd リセツト回路
JPS63167941A (ja) * 1987-01-05 1988-07-12 Mori Seiki Seisakusho:Kk マルチプロセツサ暴走停止システム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130131A (en) * 1981-02-03 1982-08-12 Nippon Denso Co Ltd Multiple computer device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130131A (en) * 1981-02-03 1982-08-12 Nippon Denso Co Ltd Multiple computer device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170622A (ja) * 1984-09-13 1986-04-11 Matsushita Electric Ind Co Ltd リセツト回路
JPS63167941A (ja) * 1987-01-05 1988-07-12 Mori Seiki Seisakusho:Kk マルチプロセツサ暴走停止システム

Also Published As

Publication number Publication date
JPH0157810B2 (enrdf_load_stackoverflow) 1989-12-07

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