JPS5842251A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JPS5842251A JPS5842251A JP14077381A JP14077381A JPS5842251A JP S5842251 A JPS5842251 A JP S5842251A JP 14077381 A JP14077381 A JP 14077381A JP 14077381 A JP14077381 A JP 14077381A JP S5842251 A JPS5842251 A JP S5842251A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- field
- groove
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Weting (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14077381A JPS5842251A (ja) | 1981-09-07 | 1981-09-07 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14077381A JPS5842251A (ja) | 1981-09-07 | 1981-09-07 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5842251A true JPS5842251A (ja) | 1983-03-11 |
JPS6355780B2 JPS6355780B2 (xx) | 1988-11-04 |
Family
ID=15276411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14077381A Granted JPS5842251A (ja) | 1981-09-07 | 1981-09-07 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5842251A (xx) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4939951A (en) * | 1987-07-14 | 1990-07-10 | Nihon Plast Co., Ltd. | Impact absorbing structure for use in steering wheels and the like |
US5899727A (en) * | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US5904539A (en) * | 1996-03-21 | 1999-05-18 | Advanced Micro Devices, Inc. | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5981357A (en) * | 1996-04-10 | 1999-11-09 | Advanced Micro Devices, Inc. | Semiconductor trench isolation with improved planarization methodology |
EP1182699A2 (de) * | 2000-08-22 | 2002-02-27 | Infineon Technologies AG | Verfahren zur Bildung eines dicken dielektrischen Gebietes in einem Halbleitersubstrat |
WO2001084602A3 (en) * | 2000-05-03 | 2002-04-04 | Maxim Integrated Products | Method of forming a shallow and deep trench isolation (sdti) suitable for silicon on insulator (soi) substrates |
JP2006319296A (ja) * | 2005-05-11 | 2006-11-24 | Hynix Semiconductor Inc | 半導体素子の素子分離膜およびその形成方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10960894B2 (en) * | 2018-12-13 | 2021-03-30 | Waymo Llc | Automated performance checks for autonomous vehicles |
JP7165093B2 (ja) | 2019-03-29 | 2022-11-02 | 本田技研工業株式会社 | 車両制御システム |
-
1981
- 1981-09-07 JP JP14077381A patent/JPS5842251A/ja active Granted
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4939951A (en) * | 1987-07-14 | 1990-07-10 | Nihon Plast Co., Ltd. | Impact absorbing structure for use in steering wheels and the like |
US5904539A (en) * | 1996-03-21 | 1999-05-18 | Advanced Micro Devices, Inc. | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties |
US5981357A (en) * | 1996-04-10 | 1999-11-09 | Advanced Micro Devices, Inc. | Semiconductor trench isolation with improved planarization methodology |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5899727A (en) * | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US6353253B2 (en) | 1996-05-02 | 2002-03-05 | Advanced Micro Devices, Inc. | Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
WO2001084602A3 (en) * | 2000-05-03 | 2002-04-04 | Maxim Integrated Products | Method of forming a shallow and deep trench isolation (sdti) suitable for silicon on insulator (soi) substrates |
EP1182699A2 (de) * | 2000-08-22 | 2002-02-27 | Infineon Technologies AG | Verfahren zur Bildung eines dicken dielektrischen Gebietes in einem Halbleitersubstrat |
EP1182699A3 (de) * | 2000-08-22 | 2007-01-31 | Infineon Technologies AG | Verfahren zur Bildung eines dicken dielektrischen Gebietes in einem Halbleitersubstrat |
JP2006319296A (ja) * | 2005-05-11 | 2006-11-24 | Hynix Semiconductor Inc | 半導体素子の素子分離膜およびその形成方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS6355780B2 (xx) | 1988-11-04 |
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