JPS5834950B2 - 集積回路の製造方法 - Google Patents

集積回路の製造方法

Info

Publication number
JPS5834950B2
JPS5834950B2 JP56091010A JP9101081A JPS5834950B2 JP S5834950 B2 JPS5834950 B2 JP S5834950B2 JP 56091010 A JP56091010 A JP 56091010A JP 9101081 A JP9101081 A JP 9101081A JP S5834950 B2 JPS5834950 B2 JP S5834950B2
Authority
JP
Japan
Prior art keywords
layer
silicon
windows
substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56091010A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5727053A (en
Inventor
ヨアネス・ヨセフ・マリア・コーメン
ロエロフ・ヘルマン・ビレム・サルテルス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPS5727053A publication Critical patent/JPS5727053A/ja
Publication of JPS5834950B2 publication Critical patent/JPS5834950B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10W10/0124—
    • H10W10/021—
    • H10W10/13—
    • H10W10/20—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP56091010A 1980-06-18 1981-06-15 集積回路の製造方法 Expired JPS5834950B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/160,668 US4317690A (en) 1980-06-18 1980-06-18 Self-aligned double polysilicon MOS fabrication

Publications (2)

Publication Number Publication Date
JPS5727053A JPS5727053A (en) 1982-02-13
JPS5834950B2 true JPS5834950B2 (ja) 1983-07-29

Family

ID=22577888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56091010A Expired JPS5834950B2 (ja) 1980-06-18 1981-06-15 集積回路の製造方法

Country Status (8)

Country Link
US (1) US4317690A (enExample)
JP (1) JPS5834950B2 (enExample)
AU (1) AU539214B2 (enExample)
CA (1) CA1157964A (enExample)
DE (1) DE3123610A1 (enExample)
FR (1) FR2485261A1 (enExample)
GB (1) GB2078443B (enExample)
NL (1) NL8102879A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4359817A (en) * 1981-05-28 1982-11-23 General Motors Corporation Method for making late programmable read-only memory devices
US4358889A (en) * 1981-05-28 1982-11-16 General Motors Corporation Process for making a late programming enhanced contact ROM
US4887135A (en) * 1982-02-09 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Dual level polysilicon single transistor-capacitor memory array
DE3274699D1 (en) * 1982-09-20 1987-01-22 Itt Ind Gmbh Deutsche Method of making a monolithic integrated circuit with at least one bipolar planar transistor
US5923985A (en) * 1987-01-05 1999-07-13 Seiko Instruments Inc. MOS field effect transistor and its manufacturing method
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten
US6675361B1 (en) * 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
US5671397A (en) * 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US5604141A (en) * 1994-03-15 1997-02-18 National Semiconductor Corporation Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction
JP4505349B2 (ja) * 2005-02-28 2010-07-21 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
CN112048707B (zh) * 2020-04-22 2022-08-12 北京航天控制仪器研究所 一种薄膜图形化夹具工装及其应用方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US3841926A (en) * 1973-01-02 1974-10-15 Ibm Integrated circuit fabrication process
US4058419A (en) * 1974-12-27 1977-11-15 Tokyo Shibaura Electric, Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4151019A (en) * 1974-12-27 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
JPS5193874A (en) * 1975-02-15 1976-08-17 Handotaisochino seizohoho
GB1543845A (en) 1975-05-27 1979-04-11 Fairchild Camera Instr Co Production of a narrow opening to a surface of a material
US4075045A (en) * 1976-02-09 1978-02-21 International Business Machines Corporation Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
FR2351502A1 (fr) * 1976-05-14 1977-12-09 Ibm Procede de fabrication de transistors a effet de champ a porte en silicium polycristallin auto-alignee avec les regions source et drain ainsi qu'avec les regions d'isolation de champ encastrees
DE2639039A1 (de) * 1976-08-30 1978-03-02 Siemens Ag Verfahren zur herstellung eines integrierten mos-bausteins mit schaltkreisen, insbesondere speicherzellen, in doppel-silizium-gate-technologie
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
US4142926A (en) * 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication

Also Published As

Publication number Publication date
US4317690A (en) 1982-03-02
FR2485261B1 (enExample) 1983-12-09
JPS5727053A (en) 1982-02-13
GB2078443A (en) 1982-01-06
GB2078443B (en) 1984-04-11
AU7183281A (en) 1981-12-24
AU539214B2 (en) 1984-09-13
DE3123610A1 (de) 1982-04-08
CA1157964A (en) 1983-11-29
FR2485261A1 (fr) 1981-12-24
NL8102879A (nl) 1982-01-18

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