JPS5833967B2 - Microprocessor operation monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for monitoring the operation of a microprocessor system.

Microcomputer systems often use a direct memory access (DMA) mechanism for data transfer between external devices and memory, but the microcomputer system's bus request signal may turn on due to some unknown reason. If left unchecked, the microcomputer system would hang up, and it was necessary to find some way to release the hang-up condition.

Furthermore, means for detecting program loops and the like is also required during software debugging.

The present invention relates to operation monitoring of a microcomputer system including a program roof and the like.

Conventionally, the method of monitoring the operating state of a microcomputer system has been to install an external hard timer and monitor a specific signal over time.

This method has the disadvantage that time monitoring is not optimized because the timer value is fixed in terms of hardware, and if it were possible to set several types of timer values for each specific signal in terms of hardware, the amount of time would increase.

Another drawback is that even if time monitoring is not required programmatically, it generally cannot be easily changed.

The objects of the present invention are (1) a microcomputer system;
The main objective is to realize the monitoring of the operating state of a microprocessor in a simple manner.

(2) The monitoring time and monitoring processing steps can be set arbitrarily by the program.

The main points of the present invention are a means for supplying a timing signal through a gate, a timer control unit that switches the timing signal between enabled (opens the gate) and disabled (closes the gate) according to the I10 instruction, and an I10 instruction. A monitoring section consisting of a timer counter is set to an arbitrary timer value and counted by the timing signal from the above gate, and monitoring is started by presetting the contents of the counter from the program to ensure normal processing steps and operations. When the counter and the monitoring gate are completed, monitoring is stopped by switching the counter and the monitoring gate to the non-monitoring side, and an abnormality is detected when a signal from the counter is generated before switching to the non-monitoring side.

FIG. 1 is a block diagram of an embodiment of the present invention and a configuration diagram showing the connection to an applied microcomputer system.

In Figure 1, μpc is a microprocessor; μpc
The data bus (μpcDATABUs) and address bus (μpc address bus) from
OW, RAM) and a monitoring unit SUP for monitoring the operation of the microcomputer system shown in FIG. 1 are connected.

Further, in FIG. 1, the timer control unit (CTL) is a part that controls whether or not to perform monitoring, and controls the timer switch (SW) to enable or disable the time monitoring timing signal (TIM). This is done by

The CTL is connected to the data bus and address bus of the μpc and can be accessed directly from the μpc using the I10 instruction.

The timer counter (CNT) is an n-bit counter that controls the count of the timer value, and is connected to the .mu.pc data bus, and can set the monitoring time-timer value using the I10 instruction.

The timer switch (SW) section is a section that switches the counter operation timing signal to be enabled or disabled according to the contents of the CTL section.

The command control unit (CMDCTL) is μpc's I10.
This is a part that controls whether the data on μpcDATABUs is loaded into the CTL section or the CNT section according to an instruction.

The abnormality detection section (ALMDTC') detects an abnormality and performs abnormality detection processing based on a signal from the counter section, and performs processing for stopping the microcomputer system or returning the system to its initial state.

FIG. 2 shows the configuration of the timer counter section.

In this embodiment, in order to reduce the burden on the program and the amount of hardware, the CTL section and the CNT section are integrated and have the same bus width as the .mu.pc data bus.

In Figure 2, the monitoring team/undesignated section corresponds to the CTL that controls the timer switch section, and the data bit is 1.
When it is 1", it indicates that monitoring is not possible, and when it is "O", it indicates that it is not possible.

Timer counter (CNT section) when the monitorable specification section is enabled.
Monitoring is controlled by incrementing the contents set in 1+1" or 1-1" each time a timer timing signal arrives.

A schematic processing procedure is shown in FIGS. 3 and 4.

When the program requires monitoring, the I10 instruction sets the monitoring time value in the CNT section and data with the monitoring enable bit set to 11'' in the CTL section.

Hardware processing and program processing are executed, and the counter timer operates at the same time.

That is, the contents of the timer counter are updated using a predetermined timer timing signal.

When the program detects the end of a predetermined process (when exiting a process step), data with the monitorable bit set to 10'' is set in the CTL section using the I10 instruction, thereby stopping monitoring.

The contents of the counter timer need only be set at the start of monitoring, and there is no need to reset them.

If the counter timer overflows or underflows before the processing step is skipped, the abnormality detection unit ALMDTC determines that the system is abnormal and performs predetermined abnormality processing, such as stopping the timing or returning the system to the initial state. Performs processing such as lighting an abnormality detection lamp.

As explained above, the present invention has the following effects.

(1) μpc can be monitored using simple hardware.

(2) Any monitoring time can be set for any processing step, facilitating monitoring, debugging, etc. of the microcomputer system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a counter timer, and FIGS. 3 and 4 are diagrams showing a schematic processing procedure. μpc...Microprocessor, ROM...
...Memo IJ, RAM...Memo IJ, CMD
CTL...Command control unit, CTL...
・Timer control section, CNT...Timer counter section, SW...Timer switch section, ALMDTC・
...Anomaly detection section.

Claims (1)

[Claims] 1. In a microcomputer system in which a microprocessor, a memory, and a plurality of I10 ports are connected to a common bus, a microcomputer system is connected to the common bus, and an arbitrary monitoring value is set by an I10 instruction from the microprocessor, and a timing signal is received. a timer counter section that counts based on the timing signal;
a timer control unit that controls whether to enable or disable the operation of the timer counter unit according to a zero instruction; and an abnormality detection unit that detects an abnormality when the count of the timer counter unit reaches the monitoring value. 1. A microprocessor operation monitoring system that monitors the operation of the microcomputer system.