JPH05257752A - Operation abnormality detecting system for cpu - Google Patents

Abstract

PURPOSE:To detect the operation abnormality of a central processing unit(CPU) without changing a program in a control system using the CPU. CONSTITUTION:On an address bus 2 of a CPU 1, a monitor device 4 having a timer 7 inside it is provided. A control part 6 of the monitor device 4 monitors the access from the CPU 1 to the specified address of a memory 3 through an address input part 5. When the access to the specified address is detected, the timer 7 is reset and when this timer 7 exceeds a value decided in advance, the operation abnormality of the CPU 1 is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program control system using a central processing unit, which stops processing due to a hardware failure of the CPU itself and CP.
The present invention relates to a method of monitoring a CPU operation abnormality due to an inconvenience of a program operating on U.

[0002]

2. Description of the Related Art Conventionally, in this type of operation abnormality monitoring system,
The monitoring device that monitors the normality of the CPU has a timer inside, and monitors that this timer exceeds a predetermined value.
The program on the CPU periodically issues a timer reset instruction to the monitoring device. When the monitoring device receives a timer reset instruction from the CPU, the monitoring device resets the timer value to zero. C
When PU stops processing or becomes abnormal in operation, C
Since the PU cannot issue a timer reset instruction to the monitoring device, the value of the timer in the monitoring device exceeds the predetermined value. The monitoring device detects an abnormal operation of the CPU when the value of the timer exceeds a certain value, that is, when the timer reset instruction is not received from the CPU for a certain time.

[0003]

As described above, in the conventional method, the CPU has to instruct the monitoring device to reset the timer every fixed time. That is, when detecting an abnormal operation of the CPU,
In addition to installing a monitoring device as hardware, C
The program running on the PU needs to have a function of issuing a timer reset instruction to the monitoring device at regular intervals. If the program to be used does not have the function to issue the timer reset instruction, it is necessary to add the function to the program, but it is generally difficult to add the function to the program. There is also a problem that it is impossible to add a function for sending a timer reset instruction to a program due to copyright problems.

[0004]

SUMMARY OF THE INVENTION An operation abnormality detecting method for a central processing unit according to the present invention comprises a monitoring device having a timer internally provided on an address bus of the central processing unit, and a memory by the central processing unit. Access to a specific address is monitored, and when the access to the specific address is detected, the timer is reset, and when the timer exceeds a predetermined value, it is determined that the central processing unit is malfunctioning. It is a configuration that does.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
3 is a flowchart showing the operation of the control unit 6 of the monitoring circuit 4 in the above configuration.

In FIG. 1, the CPU 1 is an address bus 2
The memory 3 is accessed through. The control unit 6 of the monitoring device 4 pulls in the address bus 2 via the address input unit 5, monitors the data on the address bus 2, and
When the CPU1 is connected to the reset terminal 8 of U1 and an abnormal operation of the CPU1 is detected when the timer exceeds a certain value, the reset terminal 8 is activated and the reset operation of the CPU1 is performed, and the restart process is automatically started. To do.

Next, the processing procedure will be described with reference to FIG. The control unit 6 of the monitoring device 4 reads the address on the address bus 2 through the address input unit 5 (S1: step 1). If the address can be read, the control unit 6 proceeds from step 2 to step 3. In step 3, the input address is compared with the specific monitoring target address, and if they match, the process proceeds to step 4.

In step 4, the timer 7 is cleared to 0 and the process returns to step 1. If no address is input in step 2 or if the address input in step 3 does not match the monitoring target address, the process proceeds to step 5. In step 5, the timer value is read from the timer 7 and the timer value is compared with a predetermined constant value (step 6).

If the timer value does not exceed the fixed value in step 6, the process returns to step 1. If the timer value exceeds the predetermined value in step 6, it is determined that an abnormal operation of the CPU has been detected, and the process proceeds to step 7. Step 7
Then, the reset terminal 8 of the CPU 1 is activated and the CPU
Reset operation 1 is performed. Next, the timer 7 is cleared to 0 (step 8) and the process returns to step 1.

[0010]

As described above, according to the present invention, it is possible to detect the abnormal operation of the CPU without changing the program. This has an effect that an abnormal operation of the CPU can be detected even when the existing program or the commercially available program is used as it is.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of a control unit 6 in the configuration of FIG.

[Explanation of symbols]

 1 CPU 2 Address Bus 3 Memory 4 Monitoring Device 5 Address Input Unit 6 Control Unit 7 Timer 8 Reset Terminal

Claims (1)

[Claims] 1. A monitoring device having a timer is provided on the address bus of the central processing unit, and the access to the specific address to the memory by the central processing unit is monitored to detect the access to the specific address. In this case, the timer is reset, and when the timer exceeds a predetermined value, it is determined that the operation of the central processing unit is abnormal.