JP2699761B2 - Microcomputer external output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer external output circuit for preventing an erroneous output during a runaway of a CPU (microprocessor).

[0002]

2. Description of the Related Art Generally, a microcomputer external output circuit is a circuit in which a CPU and a holding circuit for holding an output signal from the CPU are connected via a bus.

On the other hand, a watchdog timer circuit is used to monitor whether or not the CPU has run away. This watchdog timer circuit causes the CPU to output a signal at a certain interval time, monitors the signal, determines whether the interval time is within a predetermined reference time, and determines that the CPU has runaway if it is longer than the reference time. Judgment is made and an abnormality detection signal is output.

Conventionally, an abnormality detection signal of this watchdog timer circuit is inputted to a CPU, and when the CPU goes out of control, the CPU is stopped so that a signal is not output from the CPU to a holding circuit, and an erroneous output of an external output circuit is detected. Had been prevented.

[0005]

In this conventional circuit, the abnormality detection signal of the watchdog timer circuit is provided by the CPU.
Was output only for For this reason, it is possible to stop the CPU during the runaway of the CPU. However, from the runaway monitoring principle of the watchdog timer circuit described above, a time longer than a predetermined reference time is required to determine runaway. If an erroneous signal is output from the CPU to the holding circuit during the period from the occurrence of the runaway to the stop of the CPU, the erroneous signal may be held by the holding circuit, and the erroneous output may be performed even when the CPU is stopped. There was sex.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microcomputer external output circuit for preventing an erroneous signal from being output to the outside even when the CPU outputs an erroneous signal during runaway of the CPU. It is.

[0007]

A CPU and a holding circuit for holding an output signal from the CPU are connected via a bus.
The CPU detects the runaway of the CPU and outputs an abnormality detection signal at the time of the runaway.
U is connected to a CPU input terminal provided for stopping.

A gate circuit is provided on the output side of the holding circuit, and the abnormality of the watchdog timer circuit is detected so that the gate of the gate circuit is closed when the CPU runs out of control and the gate of the gate circuit is opened otherwise. The signal is connected to the gate control input terminal of the gate circuit. An integrating circuit is provided on the output side of the gate circuit to respond when the input signal continues for a predetermined time or more.

[0009]

According to the present invention, by configuring the circuit as described above, even if an erroneous signal is held in the holding circuit at the time of CPU runaway, the held output is output by closing the gate of the gate circuit, and thereafter the external signal is output. Output to the gate circuit, and erroneous output held by the holding circuit until the gate of the gate circuit closes is prevented from being output to the outside by the integration circuit, thereby preventing erroneous output to the outside. Can be.

[0010]

FIG. 1 shows an embodiment of the present invention. Hereinafter, description will be given based on FIG. The CPU 11 is connected to a ROM 12, a RAM 13, a timer output circuit 14, and a holding circuit 15 via a microprocessor bus. The watchdog timer circuit 16 is provided for monitoring runaway of the CPU 11. The input terminal of the watchdog timer circuit 16 and the output terminal of the timer output circuit 14, the watchdog timer circuit 1
6 and a CPU input terminal provided to stop the CPU 11 are connected.

A gate circuit 17 is provided on the output side of the holding circuit 15, and an input terminal of the gate circuit 17 and the holding circuit 15 are connected.
And the gate control input terminal of the gate circuit 17 and the abnormality detection signal output terminal of the watchdog timer circuit 16 are connected. Further, an integration circuit 18 is provided on the output side of the gate circuit 17.

The CP by the watchdog timer circuit 16
In the runaway monitoring of U11, a signal is output from the CPU 11 to the timer output circuit 14 via the microprocessor bus at a certain interval time, and this signal is input to the input terminal of the watchdog timer circuit 16, and the interval time is set to a predetermined reference time. It is determined whether it is within the time. As a result, if the time is equal to or longer than the reference time, the CPU 11 determines that the runaway has occurred, and outputs an abnormality detection signal from the output terminal of the watchdog timer circuit 16.

The abnormality detection signal from the watchdog timer circuit 16 causes the gate of the gate circuit 17 to be closed and the gate of the gate circuit 17 to be stopped and the gate of the gate circuit 17 to be opened at other times. A signal for stopping the CPU 11;
Used as a gate control signal for the gate circuit 17.

With this configuration, the CPU 1
When 1 is normal, the abnormality detection signal is not output from the watchdog timer circuit 16, the gate of the gate circuit 17 is opened, and the output of the holding circuit 15 is output from the gate circuit 17. When the CPU 11 runs out of control, an abnormality detection signal is output from the watchdog timer circuit 16 to stop the CPU 11, close the gate of the gate circuit 17, and after outputting the abnormality detection signal from the watchdog timer circuit 16, hold the circuit 15. Is not output from the gate circuit 17.

The response of the output to the input of the integrating circuit 18 does not output unless the input signal continues for a predetermined time or more. The predetermined time is set as the response time of the output with respect to the input of the integration circuit 18, and is set to be equal to or longer than the reference time. Due to the integration circuit 18, the CPU 11 outputs an erroneous signal between the time when the CPU 11 goes out of control and the time when the watchdog timer circuit 16 outputs the abnormality detection signal.
5 and the erroneous signal is output from the gate circuit 17 to prevent erroneous output to the outside during that time. Therefore, when the CPU 11 runs out of control, the CPU 11 outputs an erroneous signal to the holding circuit 15, and even when the CPU 11 holds the signal, the gate circuit 17 and the integrating circuit 18 prevent the signal from being output to the outside. Erroneous output can be prevented.

The integration circuit 18 can be easily realized, and one embodiment is shown in FIG. FIG. 2 shows an integration circuit 1
8, one end of a resistor 181 is used as an input terminal, the other end of the resistor 181 is connected to the other end of a capacitor 182 having one end grounded, and a comparator 183 is provided.
And is connected to the input terminal of

[0017]

As described above, according to the present invention, erroneous output can be prevented even when the CPU runs out of control and outputs an erroneous signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microcomputer external output circuit of the present invention.

FIG. 2 is a configuration diagram of an embodiment of an integration circuit.

[Explanation of symbols]

 11 CPU (microprocessor) 15 holding circuit 16 watchdog timer circuit 17 gate circuit 18 integration circuit 181 resistor 182 capacitor 183 comparator

Claims (1)

(57) [Claims] 1. An abnormality detection signal of a watchdog timer circuit which is connected via a bus to a CPU and a holding circuit for holding an output signal from the CPU, monitors a runaway of the CPU, and outputs an abnormality detection signal at the time of the runaway. Is connected to a CPU input terminal provided for stopping the CPU, a gate circuit is provided on the output side of the holding circuit, and the gate of the gate circuit is closed when the CPU runs out of control; otherwise, the gate is closed. An integrator circuit that connects an abnormality detection signal of the watchdog timer circuit to a gate control input terminal of the gate circuit so as to open a gate of the circuit, and outputs an output when the input signal continues for a predetermined time or more at an output side of the gate circuit. A microcomputer external output circuit comprising: