JPS61224047A - Overflow warning interruption system - Google Patents

Abstract

PURPOSE:To prevent previously logged information from being overwritten and to ensure logging for warning interruption by feeding back a properly delayed warning interruption signal to a logic element to which a warning interruption signal is inputted. CONSTITUTION:The logic between overflow from a time counter 2 of a program runaway monitor timer TF 1 and the warning interruption time value from a time designator 3 is operated by an AND element 4, and a warning interruption signal PRI from the element 4 is inputted to one terminal of an AND element 6. This signal PRI from the element 6 is not only outputted from an FF 5 for warning interruption but also applied to an FF 7 for warning interruption suppression. The output of the FF 7 is fed back to the other terminal of the element 6 through a delay line 8. The signal PRI is delayed properly to prevent previously logged information from being overwritten with the signal PRI, and logging during warning interruption is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improved overflow notice interrupt method for a program runaway monitoring timer TF for monitoring the normality of program operation.

Generally, in a unified system of electronic/communication equipment, TF
When an overflow occurs, the system resets and the information about the cause of the overflow is also erased. This poses a problem when searching for bugs in the program, so in order to prevent this, information on the cause of the overflow is logged to an external storage device using a warning interrupt method immediately before system reset. There is a strong demand for a countermeasure to prevent the previous information being logged from being overwritten due to a warning interrupt caused by the same event occurring.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional overflow notice interrupt system.

In the figure, 1 is a TF, 2 is a time counter, 3 is a time designator, 4 is an AND element, and 5 is a flip-flop for advance notice interrupt.

Normally, when the clock signal CP is input to the TFI, the time counter 2 counts the signal, and if the program operation is normal, the program is cleared by inputting the clear signal CRP at regular intervals, and the time counter 2 is also canceled and the program is programmed. You can also monitor the normality of the operation. If there is an abnormality in the program operation, the clear signal CRP will not be input, so the time counter 2 will continue to register and overflow, but the advance interrupt time value of the time designator 3 will be set slightly smaller than the value at that time. When set, the AND element 4 compares the two values, and when it is determined that they are the same, sends the advance notice interrupt signal PRI to the advance notice interrupt flip-flop 5, and performs advance notice interrupt processing that logs the cause information of the overflow in the external storage device. It will be done.

[Problem that the invention seeks to solve]

However, if an overflow continues to occur during the warning interrupt processing, the same operation as above is performed again, and the previously logged information is overwritten, making it impossible to analyze the cause of the initial overflow. There is a problem.

[Means for solving problems]

The above problem is solved by monitoring the advance notice interrupt signal PRI by an AND element, and opening and closing the gate of the element in response to the output signal from the interrupt suppressing flip-flop connected to the output side of the AND element, thereby preventing further advance notice interrupts. This problem is solved by the present invention.

[Effect]

According to the present invention, if the flip-flop for interrupt suppression is set immediately when the first advance notice interrupt occurs, the gate of the AND element that monitors the notice interrupt signal PRI is closed, so that no advance notice interrupts occur successively. Even if the signal PRI is input, the interrupt operation does not occur, so it is possible to prevent further advance notice interrupts.

〔Example〕

The contents of the present invention will be specifically explained below with reference to embodiments shown in the drawings.

FIG. 1 is a block diagram of the advance notice interrupt system according to the present invention, in which 6 indicates an AND element, 7 a flip-flop for suppressing advance notice interrupts, and 8 a delay line. Note that the same reference numerals refer to the same objects throughout the plan.

In the figure, when the clock signal CP is present at TFI, the time counter 2
counts the signals, and if the program is normal, the input clear signal CRP is sent at fixed intervals.The program is cleared and the time counter 2 is also canceled, but if there is an abnormality in the program operation, the clear signal CRP is sent. Since no input is made, the time counter 2 continues to register, and the AND element 4 confirms that it matches the advance notice interrupt time value of the time designator 3, and inputs the advance notice interrupt signal PRI to the AND element 6. At this time, the AND element 6 receives the reset signal SRP according to the system initial setting, and the gate is open, so the flip-flop 5 for advance notice interrupt operates, and the cause information of the overflow can be logged to the external storage device, and the cause information for advance notice interrupt can be logged to the external storage device. Flip-flop 7 is also cented. Even if the next advance notice interrupt signal PRI is continuously input to the AND element 6 during the above advance notice interrupt processing, the gate of the AND element 6 is Since the input is determined to be at a different level and closed, the flip-flop 5 for advance notice interrupt does not operate and the previous advance notice interrupt processing is reliably performed.

Furthermore, due to the system initialization of the overflow that occurs after the advance notice interrupt flip-flop 5 becomes inoperable,
The terminal R reset signal SRP of the advance interrupt suppressing flip-flop 7 is input, and the gate of the AND element 6 is restored to its original state.

Note that the delay line 8 is connected to a flip-flop 7 for suppressing advance notice interrupts in order to ensure the operation of the flip-flop 5 for advance notice interrupts.
This is to give an appropriate delay to the signal from the gate to the AND element 6.

〔Effect of the invention〕

As described in detail above, according to the present invention, logging can be reliably performed at the time of a notice interruption due to an abnormal operation of a program.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an overflow notice interrupt method according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional overflow notice interrupt method. In the figure, 1 is a TF (program runaway monitoring timer), 2 is a time counter, 3 is a time designator, 4.6 is an AND element, 5 is a flip-flop for advance notice interrupt, 7 is a flip-flop for advance notice interrupt suppression, 8 indicates a delay line.

Claims (1)

[Claims] In a program runaway monitoring method that monitors the normality of program operation by time counting, a warning interrupt signal that foretells an overflow of the time counter due to an abnormality in program operation is input to one terminal of an AND element. An overflow notice interrupt system, characterized in that a flip-flop for suppressing notice interrupts is provided on the output side of the device, and a feedback circuit is provided for inputting the output of the flip-flop to the other side of the AND element.