JPH04283841A - Microcomputer external output circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous output in the case of the runaway of a microprocessor by the microcomputer external output circuit. CONSTITUTION:A microprocessor(CPU) 11 and a holding circuit 15 which holds the output signal from the CPU 11 are connected through a bus. The abnormality detection signal of a watchdog timer circuit 16 which monitors the runaway of the CPU 11 and outputs an abnormality detection signal in case of the runaway is connected to a CPU input terminal provided so as to stop the CPU 11. A gate circuit 17 is provided on the output side of the holding circuit 15. The output of the holding circuit 15 is connected to the input terminal of the gate circuit 17 and the abnormality detection signal of the watchdog timer circuit 16 is connected to the gate control input terminal of the gate circuit 17 so that the gate circuit 17 is closed when the CPU 11 runs away and opened when not.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer external output circuit which prevents erroneous output when a CPU (microprocessor) runs out of control.

0002

2. Description of the Related Art Generally, a microcomputer external output circuit is a circuit in which a CPU and a holding circuit for holding an output signal from the CPU are connected via a bus.

On the other hand, a watchdog timer circuit is used to monitor whether the CPU has runaway. This watchdog timer circuit outputs a signal from the CPU at a certain interval time, monitors the signal, determines whether the interval time is within a predetermined reference time, and determines that the CPU has gone out of control if it is longer than the reference time. It makes a judgment and outputs an abnormality detection signal.

Conventionally, the abnormality detection signal of this watchdog timer circuit is input only to the CPU, and when the CPU runs out of control, the
U was stopped and signals were not output from the CPU to the holding circuit to prevent erroneous output from the external output circuit.

[0005]

[Problems to be Solved by the Invention] In this conventional circuit, the abnormality detection signal of the watchdog timer circuit is
It was output only for Therefore, when the CPU runs out of control, it is possible to stop the CPU, but based on the runaway monitoring principle of the watchdog timer circuit shown above, it takes more than the interval time to determine runaway. An erroneous signal is output from the CPU to the holding circuit between the occurrence of the error and the CPU stopping, and the holding circuit holds the signal, which may lead to an erroneous output when the CPU stops.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a microcomputer external circuit that prevents the CPU from outputting an erroneous signal to the outside even when the CPU outputs an erroneous signal during a CPU runaway and is held in a holding circuit. The purpose is to provide an output circuit.

[0007]

Means for Solving the Problems A CPU and a holding circuit that holds an output signal from the CPU are connected via a bus. The abnormality detection signal of the watchdog timer circuit, which monitors the runaway of the CPU and outputs the abnormality detection signal when the CPU runs out, is sent to the CPU.
Connect to the CPU input terminal provided to stop the U.

A gate circuit is provided on the output side of the holding circuit, and abnormality detection of the watchdog timer circuit is performed so that the gate of the gate circuit is closed when the CPU runs out of control, and the gate of the gate circuit is opened at other times. A signal is connected to a gate control input terminal of the gate circuit.

[0009]

[Operation] By configuring the circuit as described above, the present invention allows even if an erroneous signal is held in the holding circuit during CPU runaway, the held output is outputted to the outside by closing the gate of the gate circuit. This prevents erroneous output to the outside.

0010

[Embodiment] An embodiment of the present invention is shown in FIG. This will be explained below based on FIG. The CPU 11 is connected to a ROM 12, a RAM 13, a timer output circuit 14, and a holding circuit 15, respectively, via a microprocessor bus. A watchdog timer circuit 16 is provided for monitoring runaway of the CPU 11. The input terminal of the watchdog timer circuit 16 and the output terminal of the timer output circuit 14, the watchdog timer circuit 16
The abnormality detection signal output terminal of the CPU 11 is connected to a CPU input terminal provided for stopping the CPU 11, respectively.

Furthermore, a gate circuit 17 is provided on the output side of the holding circuit 15, and the input terminal of the gate circuit 17 and the holding circuit 15 are connected to each other.
, the gate control input terminal of the gate circuit 17 and the abnormality detection signal output terminal of the watchdog timer circuit 16 are connected, respectively.

CP by watchdog timer circuit 16
To monitor runaway of U11, a signal is output from the timer output circuit 14 via the microprocessor bus from the CPU 11 at a certain interval time, and this signal is input to the input terminal of the watchdog timer circuit 16, and the interval time is set to a predetermined standard. Determine whether the time is within. As a result, if the reference time is exceeded, it is determined that the CPU 11 has runaway, and an abnormality detection signal is output from the output terminal of the watchdog timer circuit 16.

The abnormality detection signal from the watchdog timer circuit 16 is used to stop the CPU 11 and close the gate of the gate circuit 17 when the CPU 11 runs out of control, and to operate the CPU 11 and open the gate of the gate circuit 17 at other times. , a stop signal for the CPU 11,
It is used as a gate control signal for the gate circuit 17.

[0014] With this configuration, the CPU 1
1, no abnormality detection signal is output from the watchdog timer circuit 16, the gate of the gate circuit 17 is opened, and the output of the holding circuit 15 is output from the gate circuit 17. Further, when the CPU 11 runs out of control, an abnormality detection signal is output from the watchdog timer circuit 16 to stop the CPU 11, and the gate of the gate circuit 17 is closed, so that the output of the holding circuit 15 is not output from the gate circuit 17.

Therefore, when the CPU 11 goes out of control, the CPU
11 outputs an incorrect signal to the holding circuit 15, and the holding circuit 1
Even when the voltage is held at 5, the gate circuit 17 can prevent erroneous output.

[0016]

As described above, according to the present invention, even if the CPU goes out of control and outputs an erroneous signal, it is possible to prevent erroneous output.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a microcomputer external output circuit of the present invention.

[Explanation of symbols]

11 CPU (microprocessor) 15 Holding circuit 16 Watchdog timer circuit 17 Gate circuit

Claims (1)

[Claims] 1. An abnormality detection signal of a watchdog timer circuit that connects a CPU and a holding circuit that holds an output signal from the CPU via a bus, monitors runaway of the CPU, and outputs an abnormality detection signal when the CPU runs out of control. is connected to a CPU input terminal provided to stop the CPU, and a gate circuit is provided on the output side of the holding circuit, and when the CPU runs out of control, the gate of the gate circuit is closed, and at other times, the gate is closed. A microcomputer external output circuit characterized in that an abnormality detection signal of the watchdog timer circuit is connected to a gate control input terminal of the gate circuit so as to open a gate of the circuit.