JPS62198940A - Abnormality detecting system for controller using microcomputer - Google Patents

Abstract

PURPOSE:To decrease the number of component parts and to attain an inexpensive abnormality detecting system by attaining discrimination between a reset action done by a watchdog timer from that done by an energization detecting circuit. CONSTITUTION:When a central arithmetic processing unit CPU1 is reset owing to the abnormality occurring in a system working mode, the reset signal S4 is turned off when the time set to a differentiating circuit 12 is elapsed. Then the CPU1 reads out the memory contents of a specific address of a random access memory 2 and decides whether said memory contents are coincident or not with the data written to an address in a power supply application mode. When a reset signal produced from a watchdog timer 10 is decided, the abnormal state is recovered.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an abnormality detection method in a microcomputer-based control device that detects an abnormality by determining a reset from a watchdog timer in a microcomputer-based control device. It is.

[Prior art]

Conventionally, there has been a technique in the field of such technology as described in Publication of Practical Application No. 168801/1983.

FIG. 3 is a block diagram showing the configuration of a control device using a microcomputer described in the above-mentioned document. In the figure, 1 is a central processing unit, 2 is a random access memory (RAM) that holds data when power is applied, 3 is a read-only memory (ROM), 4 is a data bus, 5 is an input circuit, and 6 is an output circuit. The central processing unit 1, random access memory 2, read-only memory 3, input circuit 5, and output circuit 6 are interconnected through a data bus 4 to form a general microcomputer. 8 is an energization detection circuit which monitors the power supply voltage, and when the voltage exceeds a specified value, issues an energization detection signal S, and the energization detection signal S! is given to the central processing unit 1 through the OR gate 9 as a reset signal. Also, 10 is a watchdog timer, 11 is a clock pulse generator, 1
2 is a differential circuit.

The watchdog timer 10 has a predetermined time limit value set by an OR signal of the reset signal S from the output circuit 6 by the OR gate 13 and the energization detection signal S of the energization detection circuit 8, and is set by the clock pulse generator 11. A countdown is performed from this time limit value using the clock pulse.

The time-up signal S of the watchdog timer 10 is applied to the input circuit 5 and the differentiating circuit 12, where it is converted into a reset signal S, and is applied to the central processing unit 1 through the OR gate 9.

The central processing unit 1 that received the reset signal S,
The initialization process shown in FIG. 4 is executed. The central processing unit 1 reads the time-up signal S according to the initialization program stored in the read-only memory 3 and determines whether or not the time-up signal S exists (step 201). S, if not,
Initialization processing inside the device is performed (step 202), and the process moves to main processing (step 203). In step 201, if there is a time-up signal S of the watchdog timer 10, it is a reset signal of the watchdog timer 10, and the process moves to recovery processing from the abnormal state (step 204).

[Problem that the invention seeks to solve]

However, in a control device using a microcomputer with the above configuration, the output line of the watchdog timer 10 is processed by central processing in order to distinguish between a reset due to power-on and a reset from the watchdog timer 10 due to abnormal operation. When using a 1-step microcomputer that needs to be read by the device 1 and has a built-in watchdog timer 10 and is reset by time-up, or a watchdog timer 10 with an energization detection circuit, the above discrimination circuit can be added externally. The problem was that it had to be done.

The present invention has been made in view of the above points, and when a microcomputer with a built-in watchdog timer or a watchdog timer with a power-on detection circuit is used, the watchdog reset due to power-on reset and abnormal operation. To provide an inexpensive and flexible determination method that does not require adding a new L determination circuit for reset due to time-up of a timer.

[Means for solving problems]

In order to solve the above problems, we developed a random access memory that retains data only when power is applied, a read-only memory that stores a program, a central processing unit that operates with the program, and input of control signals between the controlled system and the control system. An input/output circuit that performs output, an energization detection circuit that outputs a reset signal to the central processing unit when the power is energized, and a power supply detection circuit that counts clock pulses while being reset by a control signal from the output circuit according to instructions from the central processing unit, and performs time-up. In a microcomputer-based control device equipped with a watchdog timer that issues a reset signal to the central processing unit at certain times, the reset signal from the watchdog timer stored in the read-only memory or the reset signal from the energization detection circuit A program to be started determines whether specific data has been written to a specific address of the random access memory, and if it has been written, a reset is made by the automatic knob timer, and if no data has been written. If the case is a reset by the energization detection circuit, then by writing the specific data to the specific address, the reset by the energization detection circuit and the watchdog can be performed.
The system is configured to distinguish between a reset caused by a timer, determine that a reset caused by a watchdog timer is abnormal, and proceed to recovery processing from the abnormal state.

[Effect]

With the above configuration, the program activated by the reset signal from the watchdog timer distinguishes between a reset caused by the energization detection circuit and a reset caused by the watchdog timer, and when a reset is caused by the watchdog timer. This eliminates the need for wiring to input the output signal of the watchdog timer to the central processing unit. When the watchdog timer 10 with a detection circuit is used, it becomes possible to detect an abnormality in the device without adding an external circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a microcomputer-based control device according to the present invention. In the same figure, the third
Parts with the same reference numerals as in the figure indicate the same parts, and the central processing unit 1, random access memory 2, input circuit 5, and output circuit 6 are interconnected through a data bus 4 to form a general microcomputer. Various input signals are input from the controlled system 7 to the input circuit 5.
The output circuit 6 outputs various control signals to the controlled system 7, and the energization detection circuit 8 emits an energization detection signal S when the power supply voltage exceeds a specified value. The point that the reset signal is given to the central processing unit 1 is the same as that of the control device shown in FIG. 3 above. The watchdog timer 10 also receives a reset signal S from the output circuit 6 and a energization detection signal S from the energization detection circuit 8 .

This occurs when a predetermined time limit value is set and the countdown is performed from this set time limit value according to the clock pulse from the clock pulse generator 11, and when the reset signal S is no longer output and the counter reaches O. This controller is also similar to the control device shown in FIG. 3 in that the time-up signal S of the watchdog timer 10 is applied to the differentiating circuit 12, which converts it into a reset signal, and sends it to the central processing unit 1 through the OR gate 9. be.

The hardware difference between the microcomputer-based control device according to the present invention and the conventional device shown in FIG. 3 is that in FIG. However, in the device shown in FIG. 1, the time-up signal S is not input to the input circuit 5.

When the microcomputer-based control device shown in FIG. Perform the initialization process shown in .

When the microcomputer-based control device is powered on, the energization detection circuit 8 supplies the energization detection signal S to the central processing unit 1 as a power set signal. When the energization detection circuit 8 turns off the reset signal after the set time has elapsed, the watchdog timer 10 starts counting down, and at the same time, the central processing unit 1 starts controlling according to the processing flow shown in FIG. First, the storage contents of a specific address 1 in the random access memory 2 are read out. The read data is designated as data 2, and data that does not appear in the process of changing the contents of the random access memory 2 by turning off the power is designated as data 1.
Then, it is determined whether the data 2 matches data 1 (step 101). At this point, since the power has just been turned on, the data 1 and data 2 do not match, and the process moves to initializing the internal state (step 102), and the data 1 is written to address 1 of the random access memory 2 (step 103). ), the program moves to the main routine (step 104).

Next, when the central processing unit 1 is reset because the reset signal Sl is not sent from the output circuit 6 to the watchdog timer 10 due to an abnormality in the operating system, the preset time in the differentiating circuit 12 After the elapse of time, the reset signal S4 is turned off, and the central processing unit 1 starts controlling according to the processing flow shown in FIG. That is, data 2 stored at address 1 of random access memory 2 is read out, and it is determined whether it matches data 1 (
Step 101). Since the data 2 read at this time is the data 1 written to the address 1 in the power-on processing, the read data 2 and data 1 match, and it is determined that this is a reset caused by the watchdog timer 10. , move on to recovery processing from the abnormal state (step 1)
05).

By configuring the control device using a microcomputer as described above, there is no need to connect the time-up signal of the watchdog timer 10 to the input circuit 5.
This means that the number of ports in the input circuit 5 can be reduced. Also,
A 1-chip microcomputer with a built-in watchdog timer 10 that resets due to time-up,
When using the watchdog timer with the energization detection circuit 8, there is no need to add a new circuit for reset determination.

〔Effect of the invention〕

As explained above, according to the present invention, the watchdog
It is no longer necessary to connect the timer time-up signal to the input circuit, and the number of input circuit ports can be reduced.In addition, it is possible to use a one-chip microcomputer that has a built-in watchdog timer and is reset by time-up, or a watchdog with a power detection circuit. - When using a timer, excellent effects such as a reduction in the number of parts and the ability to construct an inexpensive system can be obtained without adding a new circuit for reset determination.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a microcomputer usage control device according to the present invention, FIG. 2 is a flowchart showing the flow of its initialization process, and FIG. 3 shows the configuration of a conventional microcomputer usage control device. The block diagram, FIG. 4, is a flowchart showing the flow of the initialization process. In the figure, 1... Central processing unit, 2... Random access memory, 3... Read only memory, 4
...Data bus, 5...Input circuit, 6...
Output circuit, 7... Controlled system, 8... Energization detection circuit, 9... OR gate, 10... Watchdog timer, 11... Clock pulse generator, 12
... Differential circuit, 13 ... OR gate.

Claims (1)

[Claims] Random access memory that retains data only when power is applied, read-only memory that stores a program, central processing unit that operates on the program, input/output circuit that inputs and outputs control signals to and from the controlled system, and power supply. An energization detection circuit outputs a reset signal to the central processing unit when energized, and a clock pulse is counted while being reset by a control signal from the output circuit according to instructions from the central processing unit, and reset to the central processing unit when time is up. In a microcomputer-based control device equipped with a watchdog timer that emits a signal, the random access is performed by a program stored in the read-only memory and activated by a reset signal from the watchdog timer or a reset signal from the energization detection circuit. Determine whether or not specific data has been written to a specific address of the memory, and if it has been written, the watchdog timer will be reset, and if it has not been written, the energization detection circuit will be reset, and thereafter. An abnormality detection method in a microcomputer-based control device, characterized in that a reset by the energization detection circuit and a reset by a watchdog timer are determined by writing the specific data to the specific address.