JPS59103121A - Information processor - Google Patents

Abstract

PURPOSE:To attain the parallel DMA processing without discontinuing the CPU processing by providing a bus control circuit between the internal bus of a board processor and the external bus of a peripheral device and having connection or disconnection between both buses by turning on and off said control circuit. CONSTITUTION:An external bus 7 is connected to a board processor 1, and a memory access interface 8, an external peripheral device 9 and a main memory 10 are connected directly to the bus 7. An internal bus 6 is provided to the processor 1, and a CPU2, a memory 3, an input/output device 4 and a buffer 5 are connected to the bus 6. Then the buffer 5 is connected to the bus 7. The buffer 5 is provided with a transistor-transistor logic TTL circuit and undergoes gate control by the CPU2 as a 3-state buffer. Then the buses 6 and 7 are connected or disconnected to each other to perform the parallel processing without discontinuing the processing of the CPU2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device having a bidirectional bus for data transfer.

Conventionally, the central processing unit (CPU), memory, input/output boards that control input/output data from peripheral devices, etc. are integrated into one board, and the input/output board is connected to this board by a single common bus. In an information processing device that includes peripheral devices and a main memory device, in the case of the so-called direct memory access (DMA) method in which the peripheral device transfers information with the main memory device connected to the board, an external A request signal (HOLD signal) is applied to save the address currently being executed and temporarily stop the central processing unit, and direct memory access (DMA) is performed with the bus in the board in a choked state.

For this reason, while direct memory access is being performed, the internal bus within the board is occupied by DMA operations, and the central processing unit's operation is halted during that time, so even if processing can be executed within the board, the processing is forcibly interrupted. This had the disadvantage of slowing down the processing speed.

An object of the present invention is to provide an information processing device that can perform parallel execution without stopping CPU processing even in the case of such DMA operations.

The present invention provides a CPU, a first memory, and an internal common bus that interconnects them in one unit, has a peripheral device and a second memory outside this unit, and has a peripheral device and a second memory outside the unit. The memories of the unit are commonly interconnected by an external common bus outside the unit, and a bus system is provided between the internal common bus and the external common bus.Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. . FIG. 1 is a block diagram of this embodiment. The Sl board processing device 1 includes a central processing unit 2, a memory 3, an input/output device 4, and a buffer 5, and has a complete information processing capacity (1 Uni Soto).

The data transfer bus is divided into an internal common bus 6 and an external common bus 7, which are independent of each other, via a buffer 5. Further, external peripheral devices such as a deep memory access interface, an ACE 8, an external peripheral device 9, and a main storage device 10 are connected to the external common bus 7, so that complex program processing can be executed. The relationship between the internal bus 6 and external bus 7 in the information processing device with this configuration is shown below (5) ~
(It can be divided into four types of mouth movements.

The operations (5) to (D) will be explained below with reference to FIGS. 2 to 5. In the drawing, broken lines indicate buses that are not in use, and diagonal lines surrounded by solid lines indicate buses that are in use.

(5) In FIG. 2, the l-board processing device forming one unit is separated from the external bus and executes its own processing within the board. At this time, the CPU 2 controls the buffer 5 to close, and the central processing unit 2 uses the internal bus 6 within the board to execute processing between the memory 3 and the input/output device 1, and the external bus. Leave it vacant.

(b) In FIG. 3, the l-board processing device J is performing data transfer with an external peripheral device, for example, the main storage device 10. At this time, in order for the central processing unit 2 to transfer data with the main storage device 10 or the input/output devices 8 and 9, the buffer 5 is opened and the external bus 7 and the internal bus 6 are connected and used.

(C) In FIG. 4, the external bus 7 is used for DMA transfer, and during that time, processing within the board (processing that requires the use of the external bus 7) is temporarily suspended, and the central processing unit 2 is in a waiting state. At this time, D
If MA transfer command is given priority and is interrupted, external bus 7
is occupied by the input/output devices 8, 9 and the main memory 10, and the central processing unit 2 temporarily suspends the currently executing process, saves the address indicating the process and moves it to the buffer l/register. 5 and waits until the external bus 7 becomes free.

(To) In Figure 5, 1 board processing device is connected to internal bus 6.
When the external bus 7 is used separately for executing DMA instructions. At this time, the central processing unit uses DMA
When the command is received, the buffer 5 is controlled to electrically disconnect the internal bus 6 and the external bus 7, thereby independently paralleling the processing within the one-board processing device and the processing between the external devices (for example, DMA processing). It can be operated as follows. In other words, the processing within the board controlled by the commands of the central processing unit 2 and the processing between peripheral devices executed using the external bus 7 are processed in parallel at the same time.

As described above, according to this embodiment, even if an external interrupt instruction such as a DMA instruction occurs, if the central processing unit can process it only using the internal bus 6, the processing can be stopped easily and efficiently. The processing speed can be greatly improved. In addition, by using the buffer 5 used for connection with the internal bus inside the board at the end of the board, that is, at the connection between the board and the external bus, a monitor can be added to the external bus and the processing status inside the board can be monitored externally. It can also be displayed on a monitor through the bus 7, allowing the operator to accurately grasp the program processing process.

Further, the buffer 5 may be a 3-stage (T level, 0 level, high impedance) buffer configured with a TTL (Run Sister Transistor Logic) circuit,
The control may be gate controlled by the CPU,
Alternatively, a normal transformer 7argate may be used. In this embodiment, an example was presented in which all buffers 5 were controlled when internal processing on the board and processing between external devices were performed independently, but the buffer 5 is controlled only when the processing of the central processing unit requires an external bus. may be set to open, and the others to the closed state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
5 through 5 are operational state diagrams for explaining the operation. 1...1 board processing unit, 2...central processing unit, 3...memory, 4...input/output device, 5... Buffer, 6... Internal bus, 7... External bus, 8... Direct memory access interface, 9... External peripheral device, 10... ...Main memory.

Claims (1)

[Claims] One unit includes at least a shark central processing unit, a first storage unit, and an internal common bus commonly connected to these, and a bus control circuit is provided between the internal common bus and the external common bus. , coupling the internal common bus and the external common bus by turning on and on the bus control circuit;
An information processing device characterized by controlling uncoupling.