JPH0749817A - Dma transfer controller - Google Patents

Abstract

PURPOSE:To reset an input/output device which is hungup during DMA transfer. CONSTITUTION:A central processor 1 consists of an arithmetic unit 2, a storage device 3, a data connecting device 4 which connects data of a CPU bus and a system bus, a bus controller 5, and in the data processor having an input/ output device 6 connected to the system bus, the bus controller is provided with a means which monitors time. When the DMA transfer time of the input/ output device exceeds a prescribed time, a bus abandonment signal, a system reset signal, and a bus time-out signal are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer control device in a data processing device in which a central processing unit and an input / output device are connected to a system bus.

[0002]

2. Description of the Related Art A central processing unit includes an arithmetic unit for executing arithmetic processing, a storage device for storing data necessary for arithmetic processing via a CPU bus, and a data connection for connecting data of the CPU bus and system bus. In the data processing device, which comprises a central processing unit and an input / output device capable of executing a DAM transfer, the system bus includes a device and a bus control device for controlling the bus right in the DMA transfer.
The input / output device for transfer sends a bus request signal to the system bus, and the bus control device receives the bus request signal,
Output the bus permission signal. The I / O device acquires the bus right by the bus permission, sends a bus busy signal to use the bus, and starts data transfer. After the data transfer is completed, the bus busy signal is released.

In the above-mentioned DMA transfer, the time monitoring is only the time when the data transfer execution signal is valid.

[0004]

The time monitoring of the conventional DMA transfer control device described above is only related to the execution of data transfer. Therefore, the input / output device sends a bus request signal,
There is no time monitoring until the start of data transfer, and no time monitoring from the end of data transfer until the bus busy signal is released.

Therefore, when the bus request signal, the bus permission signal, the bus busy signal malfunctions due to noise or the like during the DMA transfer execution time, or when another input / output device malfunctions, There is a problem that the central processing unit cannot operate because the I / O device hangs up with the bus right.

It is an object of the present invention to perform processing so that the central processing unit can continue processing without malfunctioning when the hang-up state occurs and the hang-up state input / output device can be used again. And

[0007]

Means for achieving the above object will be described.

FIG. 2 shows an example of system configuration.

The central processing unit 1 includes an arithmetic unit 2 for executing arithmetic processing, a storage unit 3 for storing data required for arithmetic processing via a CPU bus, and data for connecting data of the CPU bus and system bus. It is composed of a connection device 4 and a bus control device 5 for controlling the bus right in the DMA transfer.
A central processing unit 1 and an input / output device 6 capable of executing DMA transfer are connected to the system bus. The DMA transfer in the data processing device is performed by the input / output device 6 that performs the DMA transfer.
Sends a bus request signal to the system bus, and the bus controller 5 receives the bus request signal, stops the arithmetic processing of the arithmetic unit 2, and outputs a bus permission signal. I / O device 6
Acquires the bus right by permitting the bus, sends a bus busy signal to use the bus, and starts data transfer.

FIG. 1 shows the configuration of the bus control device 5.

A DMA transfer device 51 that manages the bus right such as the determination of the device that executes the DMA transfer, and a bus request signal input device 52 to which a bus request signal from the system bus is input.
A bus request signal priority determination device 53 for determining the priority of the bus request signal, a calculation stop output device 54 for outputting a calculation stop signal to the CPU bus, and a bus permission signal output device for outputting a bus permission signal, A DMA timeout monitoring device 56 that monitors the timeout time, a bus abandonment signal output device 57 that outputs a bus abandonment signal, a system reset output device 58 that outputs a system reset signal to the system bus, and a time-out to the arithmetic unit via the CPU bus. The time-out output device 59 for reporting

The time monitoring of the DMA time-out monitoring device 56 of the bus control device 5 is executed at three points as shown in the time-out monitoring of FIG.

Monitoring 1 Monitoring is performed until the bus control device 5 outputs a bus permission signal and the input / output device transmits a bus busy signal.

Monitor 2 The time from the output of the bus busy signal from the input / output device 6 to the start of data transfer is monitored.

Monitor 3 Monitors the time from the end of the data transfer by the input / output device 6 to the release of the bus busy signal.

When the DMA timeout monitoring device 56 detects that the above monitoring time has been exceeded, the DMA control device 5
1, the DMA controller 51 outputs a bus abandon signal from the bus abandon signal output device 57. Further, when the input / output device 6 of the system bus outputs the bus abandon signal but has the bus right, the system reset signal is output from the system reset output device 58 to the system bus. Further, the DMA control device 51 sends a bus abandonment signal and a bus abandonment signal, and also reports a bus timeout signal to the arithmetic unit 2 via the CPU bus at the timeout output device 59.

By the above DMA time-out monitoring, it is possible to detect that the I / O device is erroneously operating and is in the hang-up state while taking the bus right. The input / output device in the middle transition state can be eliminated, and the input / output device in the hang-up state can be initialized by outputting the system reset signal. During this time, the central processing unit is in the operation stop state, and when restarting the operation, it is found that the DMA transfer is abnormal due to the bus timeout signal, and the abnormal processing is executed. In other words, the central processing unit can continue processing without malfunctioning, and the hung-up input / output device can be restored.

[0018]

The operation flow of DMA transfer is shown in FIG.
An example of the system configuration will be described.

(Step 1) The input / output device 6 executing the DMA transfer asserts the bus request signal.

(Step 2) The bus control unit 5 detects the bus request signal, stops the arithmetic unit 2, determines the priority order, and outputs the bus permission signal corresponding to the request signal having the higher priority.

(Step 3) The input / output device 6 which executes the DMA transfer detects the bus permission signal and asserts the bus busy signal.

(Step 4) The input / output device 6 which executes the DMA transfer negates the bus request signal after asserting the bus busy signal and executes the data transfer.

(Step 5) The bus control device 5 negates the bus permission signal after detecting the bus busy signal.

(Step 6) The input / output device 6 which executes the DMA transfer negates the bus busy signal after the data transfer is completed.

In the operation flow of this DMA transfer, the DMA time-out monitoring device 56 in the bus control device 5 performs time monitoring from the assertion of the bus permission signal of the monitoring 1 (step 2) to the bus of (step 3). While the busy signal is asserted Monitor 2 (Step 3) From the bus busy signal assertion to the data transfer start of (Step 4) From the monitoring 3 (Step 4) data transfer end (Step 6) Bus busy signal is negated There are three locations in between.

FIG. 5 shows an operation flow when the DMA time-out monitoring device 56 detects a time-out.

(Step 10) The DMA timeout monitoring device 56 detects that the monitoring time has been exceeded.

(Step 11) The bus controller asserts the bus relinquish signal.

(Step 12) The input / output device detects the bus abandon signal and abandons the DMA transfer. (Step 13) The bus controller checks whether or not the bus request signal and the bus busy signal are negated in order to confirm that the I / O device DMA transfer has been abandoned.

(Step 14) If the I / O device has not abandoned the DMA transfer in (Step 13), the bus controller outputs a system reset signal.

(Step 15) The input / output device detects and initializes the system reset signal.

(Step 16) When the I / O device abandons the DMA transfer in (Step 13) and (Step 1)
When 5) is executed, the bus timeout signal is validated and reported to the arithmetic unit.

According to the above operation flow, the DMA transfer operation, the timeout monitoring, and the timing after the timeout detection are good.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a system configuration example of the present invention.

The central processing unit 1 includes an arithmetic unit 2 for executing arithmetic processing, a storage unit 3 for storing data required for arithmetic processing via a CPU bus, and data for connecting data of the CPU bus and system bus. It is composed of a connection device 4 and a bus control device 5 for controlling the bus right in the DMA transfer.
A central processing unit 1 and an input / output device 6 capable of executing DMA transfer are connected to the system bus. The DMA transfer in the data processing device is performed by the input / output device 6 that performs the DMA transfer.
Sends a bus request signal to the system bus, and the bus controller 5 receives the bus request signal, stops the arithmetic processing of the arithmetic unit 2, and outputs a bus permission signal.

The input / output device 6 acquires the bus right by the bus permission, sends a bus busy signal to use the bus, and starts data transfer.

FIG. 1 shows the configuration of the bus controller 5.

A DMA control device 51 for managing the bus right such as a device for executing the DMA transfer and a bus request signal input device 52 for inputting a bus request signal from the system bus.
A bus request signal priority determination device 53 for determining the priority of the bus request signal, a calculation stop output device 54 for outputting a calculation stop signal to the CPU bus, and a bus permission signal output device for outputting a bus permission signal, A DMA timeout monitoring device 56 that monitors the timeout time, a bus abandonment signal output device 57 that outputs a bus abandonment signal, a system reset output device 58 that outputs a system reset signal to the system bus, and a time-out to the arithmetic unit via the CPU bus. The time-out output device 59 for reporting

The time monitoring of the DMA time-out monitoring device 56 of the bus control device 5 is executed at three points as shown in the time-out monitoring of FIG.

Monitoring 1 Monitoring is performed until the bus control device 5 outputs a bus permission signal and the input / output device transmits a bus busy signal.

Monitor 2 The time from the output of the bus busy signal from the input / output device 6 to the start of data transfer is monitored.

Monitoring 3 The time from the end of data transfer by the input / output device 6 to the release of the bus busy signal is monitored.

When the DMA timeout monitoring device 56 detects that the above monitoring time has been exceeded, the DMA control device 5
1, the DMA controller 51 outputs a bus abandon signal from the bus abandon signal output device 57. Further, when the input / output device 6 of the system bus outputs the bus abandon signal but has the bus right, the system reset signal is output from the system reset output device 58 to the system bus. Further, the DMA control device 51 sends a bus abandonment signal and a bus abandonment signal, and also reports a bus timeout signal to the arithmetic unit 2 via the CPU bus at the timeout output device 59.

FIG. 4 shows an operation flow of DMA transfer.

(Step 1) The input / output device 6 executing the DMA transfer asserts the bus request signal.

(Step 2) The bus control unit 5 detects the bus request signal, stops the arithmetic unit 2, determines the priority order, and outputs the bus permission signal corresponding to the request signal having the higher priority.

(Step 3) The input / output device 6 executing the DMA transfer detects the bus permission signal and asserts the bus busy signal.

(Step 4) The input / output device 6 which executes the DMA transfer negates the bus request signal after asserting the bus busy signal and executes the data transfer.

(Step 5) The bus control device 5 negates the bus permission signal after detecting the bus busy signal.

(Step 6) The input / output device 6 which executes the DMA transfer negates the bus busy signal after the data transfer is completed.

In the operation flow of this DMA transfer, the DMA time-out monitoring device 56 in the bus control device 5 performs time monitoring from the assertion of the bus permission signal of the monitor 1 (step 2) to the bus of (step 3). While the busy signal is asserted Monitor 2 (Step 3) From the bus busy signal assertion to the data transfer start of (Step 4) From the monitoring 3 (Step 4) data transfer end (Step 6) Bus busy signal is negated There are three locations in between.

FIG. 5 shows an operation flow when the DMA timeout monitoring device 56 detects a timeout.

(Step 10) The DMA timeout monitoring device 56 detects that the monitoring time has been exceeded.

(Step 11) The bus controller asserts the bus relinquish signal.

(Step 12) The input / output device detects the bus abandon signal and abandons the DMA transfer. (Step 13) The bus controller is the input / output device DMA
Investigate whether the bus request signal and the bus busy signal are negated to confirm that the transfer was abandoned.

(Step 14) If the I / O device has not abandoned the DMA transfer in (Step 13), the system reset signal is output from the bus controller.

(Step 15) The input / output device detects and initializes the system reset signal.

(Step 16) When the I / O device abandons the DMA transfer in (Step 13) (Step 1)
When 5) is executed, the bus timeout signal is validated and reported to the arithmetic unit.

By the above configuration, operation flow and DMA timeout monitoring, it is possible to detect that the I / O device 6 is erroneously operating and is in the hang-up state while taking the bus right. DMA by signal output
The I / O device 6 in the transition state during transfer can be eliminated, and the I / O device 6 in the hang-up state can be initialized by outputting the system reset signal. During this time, the central processing unit 1 is in the operation stop state, and when restarting the operation, it is found that the DMA transfer is abnormal due to the bus timeout signal, and the abnormal processing is executed. In other words, the central processing unit 1 can be continuously processed without malfunctioning, and the hung-up I / O device 6 can be processed again.

Next, application examples of the above device will be described.

Even when an I / O device capable of executing DMA transfer is connected to the CPU bus in the central processing unit, if the I / O device detects that the DMA timeout monitoring device has exceeded the monitoring time during DMA transfer, The DMA control device can eliminate the input / output device in the transition state during the DMA transfer by outputting the bus abandonment signal from the bus abandonment signal output device.

In the above device, when the DMA timeout monitoring device detects that the monitoring time is exceeded, it reports to the DMA control device, the DMA control device outputs a bus abandonment signal from the bus abandonment signal output device, and the system further When the bus input / output device owns the bus right, the system reset signal is output from the system reset output device to the system bus. However, the input / output device can be recovered by only sending the bus abandon signal or the system reset signal.

[0064]

As is apparent from the above description, according to the present invention, the time monitoring of the conventional DMA transfer control device is only for the data transfer execution, whereas the I / O device is the bus request signal. By sending time and starting data transfer, and by monitoring the time from the end of data transfer to the release of the bus busy signal.
If the bus request signal, bus enable signal, or bus busy signal malfunctions due to noise, etc. within the transfer execution time,
Further, the problem that the central processing unit cannot operate because the I / O device hangs up with the bus right when another I / O device is erroneously operated can be solved. In other words, when the input / output device is in the hang-up state, the central processing unit can continue processing without malfunctioning, and the input / output device in the hung-up state can be restored so that it can be used again. Therefore, it becomes possible for the data processing device to construct a system with higher reliability.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bus control device.

FIG. 2 is a diagram showing an example of a system configuration.

FIG. 3 is a diagram showing timeout monitoring.

FIG. 4 is an operation flowchart of DMA transfer.

FIG. 5 is an operation flow diagram at the time of timeout.

[Explanation of symbols]

1 ... Central processing unit, 2 ... Arithmetic unit, 3 ... Main memory unit, 4
... data connection device, 5 ... bus connection device, 6 ... input / output device, 51 ... DMA control device, 52 ... bus request signal input / output device, 53 ... bus request signal priority determination device, 54 ... operation stop output device, 55 ... Bus permission signal output device, 5
6 ... DMA timeout monitoring device, 57 ... Bus abandonment signal output device, 58 ... System reset output device, 59 ... Butter timeout output device.

Claims (4)

[Claims] 1. A storage device for storing data necessary for arithmetic processing via a CPU bus in an arithmetic device for executing arithmetic processing on a system bus, and a data connection device for connecting data of the CPU bus and system bus. In a data processing device to which a central processing unit including a bus control device for controlling a bus right in a DMA transfer and an input / output device capable of executing a DMA transfer of a system bus are connected, a bus use enable signal is sent to the bus control device. A bus abandonment signal is transmitted which has means for time monitoring the bus busy signal and the data transfer execution signal, and abandons the ownership of the bus right when the DMA transfer time by the input / output device exceeds a specified time. The entry output device outputs a system reset signal to the system bus when the bus right is owned even if the bus abandon signal is sent, and With sending the bus abandon signal and the system reset signal, DMA transfer control apparatus characterized by reporting the timeout to the processing unit via a CPU bus. 2. A storage device for storing data required for the arithmetic processing, and a DMA transferable input / output device for inputting / outputting data required for the arithmetic processing via a CPU bus to an arithmetic device for executing the arithmetic processing on the system bus. A central processing unit comprising an output device, a data connection device for connecting the data of the CPU bus and the system bus, and a bus control device for controlling the bus right in the DMA transfer, and an input / output device capable of performing the DMA transfer of the system bus. In the data processing device to which is connected,
The bus controller is provided with means for time-monitoring a bus use permission signal, a bus busy signal, and a data transfer execution signal, and relinquishing ownership of the bus right when the DMA transfer time by the input / output device exceeds a specified time. A bus relinquish signal is sent to cause the I / O device to relinquish the bus right, and when the I / O device of the system bus has the bus right, a system reset signal is output to the system bus. A DMA transfer control device characterized in that it sends a bus abandonment signal and a system reset signal and reports a time-out to an arithmetic unit via a CPU bus. 3. An arithmetic unit for executing arithmetic processing on a system bus, via a CPU bus, a storage unit for storing data necessary for arithmetic processing, and a DMA transferable input / output unit for inputting / outputting data necessary for arithmetic processing. A central processing unit comprising an output device, a data connection device for connecting the data of the CPU bus and the system bus, and a bus control device for controlling the bus right in the DMA transfer, and an input / output device capable of performing the DMA transfer of the system bus. In the data processing device to which is connected,
The bus controller is provided with means for time-monitoring a bus use permission signal, a bus busy signal, and a data transfer execution signal, and relinquishing ownership of the bus right when the DMA transfer time by the input / output device exceeds a specified time. A DMA transfer control device characterized in that a bus abandonment signal is sent to abandon the bus right of an input / output device, and at the same time, a timeout is reported to a computing device via a CPU bus. 4. A storage device for storing data necessary for arithmetic processing via a CPU bus in an arithmetic device for executing arithmetic processing on the system bus, and a data connection device for connecting data of the CPU bus and the system bus. In a data processing device to which a central processing unit including a bus control device for controlling a bus right in a DMA transfer and an input / output device capable of executing a DMA transfer of a system bus are connected, a bus use enable signal is sent to the bus control device. A means for monitoring the bus busy signal and the data transfer execution signal is provided, and when the DMA transfer time by the input / output device exceeds a specified time, a system reset signal is output to the system bus, and at the same time, the CP
A DMA transfer control device characterized by reporting a time-out to an arithmetic unit via a U bus.